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Peter Anvin" , Russ Anderson , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: [PATCH v3 2/3] x86/platform/uv: Update TSC sync state for UV5 Date: Fri, 18 Mar 2022 17:43:03 -0500 Message-Id: <20220318224304.174967-3-mike.travis@hpe.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20220318224304.174967-1-mike.travis@hpe.com> References: <20220318224304.174967-1-mike.travis@hpe.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: HHwULhifDUkZaLVnbF7EARGsKPn2ztiA X-Proofpoint-GUID: HHwULhifDUkZaLVnbF7EARGsKPn2ztiA X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-18_14,2022-03-15_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 clxscore=1015 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203180122 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update TSC to not check TSC sync state for uv5+ as it is not available. It is assumed that TSC will always be in sync for multiple chassis and will pass the tests for the kernel to accept it as the clocksource. To disable this check use the kernel start options tsc=reliable clocksource=tsc. Signed-off-by: Mike Travis Reviewed-by: Dimitri Sivanich Reviewed-by: Steve Wahl --- v2: Update patch description to be more explanatory. --- arch/x86/kernel/apic/x2apic_uv_x.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index f5a48e66e4f5..387d6533549a 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -199,10 +199,16 @@ static void __init uv_tsc_check_sync(void) int mmr_shift; char *state; - /* Different returns from different UV BIOS versions */ + /* UV5+, sync state from bios not available, assumed valid */ + if (!is_uv(UV2|UV3|UV4)) { + pr_debug("UV: TSC sync state for UV5+ assumed valid\n"); + mark_tsc_async_resets("UV5+"); + return; + } + + /* UV2,3,4, UV BIOS TSC sync state available */ mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); - mmr_shift = - is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; + mmr_shift = is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; /* Check if TSC is valid for all sockets */ -- 2.26.2