From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests
Date: Tue, 29 Mar 2022 12:59:08 +0530 [thread overview]
Message-ID: <20220329072911.1692766-1-apatel@ventanamicro.com> (raw)
Getting unexpected guest traps while running KVM RISC-V selftests should
cause the test to fail appropriately with VCPU register dump. This series
improves handling of unexpected traps along these lines.
These patches can also be found in riscv_kvm_selftests_unexp_trap_v1 branch
at: https://github.com/avpatel/linux.git
Anup Patel (3):
KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table
KVM: selftests: riscv: Fix alignment of the guest_hang() function
KVM: selftests: riscv: Improve unexpected guest trap handling
.../selftests/kvm/include/riscv/processor.h | 12 ++++---
.../selftests/kvm/lib/riscv/processor.c | 9 +++---
tools/testing/selftests/kvm/lib/riscv/ucall.c | 31 +++++++++++++------
3 files changed, 34 insertions(+), 18 deletions(-)
--
2.25.1
next reply other threads:[~2022-03-29 7:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-29 7:29 Anup Patel [this message]
2022-03-29 7:29 ` [PATCH 1/3] KVM: selftests: riscv: Set PTE A and D bits in VS-stage page table Anup Patel
2022-04-05 7:18 ` Anup Patel
2022-03-29 7:29 ` [PATCH 2/3] KVM: selftests: riscv: Fix alignment of the guest_hang() function Anup Patel
2022-04-05 7:18 ` Anup Patel
2022-03-29 7:29 ` [PATCH 3/3] KVM: selftests: riscv: Improve unexpected guest trap handling Anup Patel
2022-04-04 4:11 ` [PATCH 0/3] Unexpected guest trap handling for KVM RISC-V selftests Mayuresh Chitale
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