[PATCH v3 0/3] x86/platform/uv: UV Kernel support for UV5

[Mike Travis <mike.travis@hpe.com>]

Send a second time on 04/04/22, sent first time on 03/18/22.

v2: Delete patch to remove SCRATCH 5 NMI support check for
    UV2 and UV3k systems with old NMI support function.

v3: Fix check BIOS NMI support mistake in Patch 1.

    Update NMI setup for UV5
	Update NMI handler to interface with UV5 hardware. This involves
	changing the EVENT_OCCURRED MMR used by the hardware and removes
	the check for which NMI function is supported by UV BIOS.  The
	newer NMI function is assumed supported on UV5 and above.

    Update TSC sync check for UV5
	Update TSC to not check TSC sync state for uv5+ as it is not
	available.  It is assumed that TSC will always be in sync for
	multiple chassis and will pass the tests for the kernel to
	accept it as the clocksource.  To disable this check use the
	kernel start options tsc=reliable clocksource=tsc.

    Log gap hole end size
	Show value of gap end in the kernel log which equates to number
	of physical address bits used by system.  The end address of
	the gap holds PA bits 56:26 which gives the range up to 64PB
	max size with 64MB of granularity.

Mike Travis (3):
  x86/platform/uv: Update NMI Handler for UV5
  x86/platform/uv: Update TSC sync state for UV5
  x86/platform/uv: Log gap hole end size

 arch/x86/kernel/apic/x2apic_uv_x.c | 20 +++++++++++++++-----
 arch/x86/platform/uv/uv_nmi.c      | 21 +++++++++++----------
 2 files changed, 26 insertions(+), 15 deletions(-)

-- 
2.26.2