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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT039.mail.protection.outlook.com (10.13.177.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5123.19 via Frontend Transport; Mon, 4 Apr 2022 20:47:33 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 4 Apr 2022 15:47:32 -0500 From: Mario Limonciello To: Joerg Roedel , Will Deacon CC: Christoph Hellwig , Marek Szyprowski , Robin Murphy , "open list:IOMMU DRIVERS" , Suthikulpanit Suravee , Hegde Vasant , "open list" , Mario Limonciello Subject: [PATCH v2 0/2] Fix issues with untrusted devices and AMD IOMMU Date: Mon, 4 Apr 2022 15:47:21 -0500 Message-ID: <20220404204723.9767-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ee9ee406-8356-40b9-5bd7-08da167c5858 X-MS-TrafficTypeDiagnostic: MWHPR12MB1839:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Apr 2022 20:47:33.9506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee9ee406-8356-40b9-5bd7-08da167c5858 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1839 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It's been observed that plugging in a TBT3 NVME device to a port marked with ExternalFacingPort that some DMA transactions occur that are not a full page and so the DMA API attempts to use software bounce buffers instead of relying upon the IOMMU translation. This doesn't work and leads to messaging like: swiotlb buffer is full (sz: 4096 bytes), total 0 (slots), used 0 (slots) The bounce buffers were originally set up, but torn down during the boot process. * This happens because as part of IOMMU initialization `amd_iommu_init_dma_ops` gets called and resets the global swiotlb to 0. * When late_init gets called `pci_swiotlb_late_init` `swiotlb_exit` is called and the buffers are torn down. This can be observed in the logs: ``` [ 0.407286] AMD-Vi: Extended features (0x246577efa2254afa): PPR NX GT [5] IA GA PC GA_vAPIC [ 0.407291] AMD-Vi: Interrupt remapping enabled [ 0.407292] AMD-Vi: Virtual APIC enabled [ 0.407872] software IO TLB: tearing down default memory pool ``` This series fixes the behavior of AMD IOMMU to enable swiotlb so that non-page aligned DMA goes through a bounce buffer. It also adds a message to help with debugging similar problems in the future. Mario Limonciello (2): iommu/amd: Enable swiotlb in all cases dma-iommu: Check that swiotlb is active before trying to use it drivers/iommu/amd/iommu.c | 7 ------- drivers/iommu/dma-iommu.c | 5 +++++ 2 files changed, 5 insertions(+), 7 deletions(-) -- 2.34.1