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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT008.mail.protection.outlook.com (10.13.175.191) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5144.20 via Frontend Transport; Tue, 5 Apr 2022 23:09:29 +0000 Received: from sp5-759chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 5 Apr 2022 18:09:23 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 07/12] KVM: SVM: Adding support for configuring x2APIC MSRs interception Date: Tue, 5 Apr 2022 18:08:50 -0500 Message-ID: <20220405230855.15376-8-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220405230855.15376-1-suravee.suthikulpanit@amd.com> References: <20220405230855.15376-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 13a8a095-fdcb-4b63-8b14-08da175956a2 X-MS-TrafficTypeDiagnostic: BN8PR12MB3044:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2022 23:09:29.7024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13a8a095-fdcb-4b63-8b14-08da175956a2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3044 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When enabling x2APIC virtualization (x2AVIC), the interception of x2APIC MSRs must be disabled to let the hardware virtualize guest MSR accesses. Current implementation keeps track of list of MSR interception state in the svm_direct_access_msrs array. Therefore, extends the array to include x2APIC MSRs. Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm/svm.c | 30 +++++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.h | 5 +++-- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index bbdc16c4b6d7..56ad9ba05111 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -89,7 +89,7 @@ static uint64_t osvw_len = 4, osvw_status; static DEFINE_PER_CPU(u64, current_tsc_ratio); #define TSC_RATIO_DEFAULT 0x0100000000ULL -static const struct svm_direct_access_msrs { +static struct svm_direct_access_msrs { u32 index; /* Index of the MSR */ bool always; /* True if intercept is initially cleared */ } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = { @@ -786,6 +786,33 @@ static void add_msr_offset(u32 offset) BUG(); } +static void init_direct_access_msrs(void) +{ + int i, j; + + /* Find first MSR_INVALID */ + for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) { + if (direct_access_msrs[i].index == MSR_INVALID) + break; + } + BUG_ON(i >= MAX_DIRECT_ACCESS_MSRS); + + /* + * Initialize direct_access_msrs entries to intercept X2APIC MSRs + * (range 0x800 to 0x8ff) + */ + for (j = 0; j < 0x100; j++) { + direct_access_msrs[i + j].index = boot_cpu_has(X86_FEATURE_X2AVIC) ? + (APIC_BASE_MSR + j) : MSR_INVALID; + direct_access_msrs[i + j].always = false; + } + BUG_ON(i + j >= MAX_DIRECT_ACCESS_MSRS); + + /* Initialize last entry */ + direct_access_msrs[i + j].index = MSR_INVALID; + direct_access_msrs[i + j].always = true; +} + static void init_msrpm_offsets(void) { int i; @@ -4765,6 +4792,7 @@ static __init int svm_hardware_setup(void) memset(iopm_va, 0xff, PAGE_SIZE * (1 << order)); iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; + init_direct_access_msrs(); init_msrpm_offsets(); supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index b53c83a44ec2..0bbbe8d6a87a 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -27,8 +27,9 @@ #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 -#define MAX_DIRECT_ACCESS_MSRS 20 -#define MSRPM_OFFSETS 16 +#define MAX_DIRECT_ACCESS_MSRS (20 + 0x100) +#define MSRPM_OFFSETS 30 + extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; extern bool intercept_smi; -- 2.25.1