Re: [PATCH v8 0/7] CTU CAN FD open-source IP core SocketCAN driver, PCI, platform integration and documentation

[Pavel Pisa <pisa@cmp.felk.cvut.cz>]

Hello Marc and others,

On Tuesday 22 of March 2022 10:22:12 Marc Kleine-Budde wrote:
> On 22.03.2022 09:18:32, Pavel Pisa wrote:
> > > The driver looks much better now. Good work. Please have a look at the
> > > TX path of the mcp251xfd driver, especially the tx_stop_queue and
> > > tx_wake_queue in mcp251xfd_start_xmit() and mcp251xfd_handle_tefif(). A
> > > lockless implementation should work in your hardware, too.
> >
> > Is this blocker for now? I would like to start with years tested base.
>
> Makes sense.

I have missed timing for 5.18 but v5.18-rc1 is out so I would be
happy if we do not miss 5.19 merge window at least with minimal version.

If we succeeds in review reasonably early we could fit with inclusion
or at least the first review round of Mataj Vasilevski's 

  https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/tree/hw-timestamping

Please, help us to finish this subsequent goal of our portfolio development.
I think that our work is valuable for the community, code can be tested
even in QEMU CAN bus subsystem which we architected as well

  https://www.qemu.org/docs/master/system/devices/can.html

I hope that it is usable for others. I have the last support call from
Magdeburg University where they use CAN emulation for some Volkswagen
projects. The Xilinx uses code for their CAN FD controllers emulation.
Thei have whole stack including mainline driver for their CAN FD controller
in mainline but on the other hand, their CAN FD is bound to Xilinx devices
emulation. But CTU CAN FD provides generic PCI integration and can be used
even on broad range of FPGAs so its emulation and matching driver provides
valuable tool even if you do not consider use its actual design on hardware.

New version of the latency tester based on CTU CAN FD timestamping
is in preparation as upgrade of original Martin Jerabek's
work done on Oliver Hartkopp's and Volkswagen call

  
https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top/wikis/uploads/56b4d27d8f81ae390fc98bdce803398f/F3-BP-2016-Jerabek-Martin-Jerabek-thesis-2016.pdf

Best wishes,

                Pavel
--
                Pavel Pisa
    phone:      +420 603531357
    e-mail:     pisa@cmp.felk.cvut.cz
    Department of Control Engineering FEE CVUT
    Karlovo namesti 13, 121 35, Prague 2
    university: http://dce.fel.cvut.cz/
    personal:   http://cmp.felk.cvut.cz/~pisa
    projects:   https://www.openhub.net/accounts/ppisa
    CAN related:http://canbus.pages.fel.cvut.cz/
    Open Technologies Research Education and Exchange Services
    https://gitlab.fel.cvut.cz/otrees/org/-/wikis/home