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From:   Michael Walle <michael@walle.cc>
To:     kavyasree.kotagiri@microchip.com
Cc:     Claudiu.Beznea@microchip.com, Manohar.Puri@microchip.com,
        Nicolas.Ferre@microchip.com, Tudor.Ambarus@microchip.com,
        UNGLinuxDriver@microchip.com, alexandre.belloni@bootlin.com,
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        linux-spi@vger.kernel.org, robh+dt@kernel.org,
        Michael Walle <michael@walle.cc>
Subject: Re: [PATCH] spi: atmel,quadspi: Define lan966x QSPI
Date:   Mon, 11 Apr 2022 16:46:19 +0200
Message-Id: <20220411144619.101883-1-michael@walle.cc>
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> > > LAN966x SoC supports 3 QSPI controllers. Each of them support
> > > data and clock frequency upto 100Mhz DDR and QUAD protocol.
> >
> > How is this IP different than microchip,sama7g5-qspi? Does this speed
> > limitation come from the IP itself or from the board that you're using?
> >
> > Neither of these instances support octal mode?
> >
> Thanks for your comments. All the three instances support only QUAD
> protocol.
> You are correct. There is no difference from sama7g5-qspi. Please ignore
> this patch. I will send next version of dt patches where I will use
> "microchip,sama7g5-qspi" for all my qspi nodes.

Are you sure? There is a max frequency property in Tudor's sama7g5-qspi
driver (200/133MHz) which doesn't match neither the LAN9668 manual (which
states 150MHz on QSPI0 and 100MHZ on QSPI1, funny enough there is no
mention of QSPI2) nor does it match the max frequency set in the downstream
linux driver (24 MHz).

-michael