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Wed, 13 Apr 2022 14:05:39 -0700 (PDT) Date: Wed, 13 Apr 2022 14:05:03 -0700 In-Reply-To: <20220413210503.3256922-1-irogers@google.com> Message-Id: <20220413210503.3256922-14-irogers@google.com> Mime-Version: 1.0 References: <20220413210503.3256922-1-irogers@google.com> X-Mailer: git-send-email 2.36.0.rc0.470.gd361397f0d-goog Subject: [PATCH 14/14] perf vendor events intel: Update goldmont event topics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Maxime Coquelin , Alexandre Torgue , Kan Liang , Xing Zhengjun , Andi Kleen , John Garry , James Clark , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Ian Rogers Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Apply topic updates from: https://github.com/intel/event-converter-for-linux-perf/ Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/goldmont/other.json | 31 +------------------ .../arch/x86/goldmont/pipeline.json | 31 ++++++++++++++++++- 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/goldmont/other.json b/tools/per= f/pmu-events/arch/x86/goldmont/other.json index e4605e636447..d888f67aa2ea 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/other.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/other.json @@ -47,34 +47,5 @@ "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", "SampleAfterValue": "203", "UMask": "0x1" - }, - { - "BriefDescription": "Unfilled issue slots per cycle", - "CollectPEBSRecord": "1", - "Counter": "0,1,2,3", - "EventCode": "0xCA", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", - "SampleAfterValue": "200003" - }, - { - "BriefDescription": "Unfilled issue slots per cycle to recover", - "CollectPEBSRecord": "1", - "Counter": "0,1,2,3", - "EventCode": "0xCA", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", - "SampleAfterValue": "200003", - "UMask": "0x2" - }, - { - "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend", - "CollectPEBSRecord": "1", - "Counter": "0,1,2,3", - "EventCode": "0xCA", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", - "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", - "SampleAfterValue": "200003", - "UMask": "0x1" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/= perf/pmu-events/arch/x86/goldmont/pipeline.json index cb9155c3836d..5dba4313013f 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json @@ -245,6 +245,35 @@ "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The event continues = counting during hardware interrupts, traps, and inside interrupt handlers. = This is an architectural performance event. This event uses a (_P)rogramm= able general purpose performance counter. *This event is Precise Event capa= ble: The EventingRIP field in the PEBS record is precise to the address of= the instruction which caused the event. Note: Because PEBS records can be= collected only on IA32_PMC0, only one event can use the PEBS facility at a= time.", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "Unfilled issue slots per cycle", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Unfilled issue slots per cycle to recover", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", + "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, { "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)", "CollectPEBSRecord": "2", @@ -379,4 +408,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -] \ No newline at end of file +] --=20 2.36.0.rc0.470.gd361397f0d-goog