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From: Miles Chen <miles.chen@mediatek.com>
To: <matthias.bgg@kernel.org>
Cc: <allen-kh.cheng@mediatek.com>, <chun-jie.chen@mediatek.com>,
	<ikjn@chromium.org>, <linux-arm-kernel@lists.infradead.org>,
	<linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <matthias.bgg@gmail.com>,
	<mturquette@baylibre.com>, <sboyd@kernel.org>,
	<weiyi.lu@mediatek.com>
Subject: Re: [PATCH] clk: mediatek: Delete MT8192 msdc gate
Date: Mon, 25 Apr 2022 15:30:54 +0800	[thread overview]
Message-ID: <20220425073054.1391-1-miles.chen@mediatek.com> (raw)
In-Reply-To: <20220422143756.14806-1-matthias.bgg@kernel.org>

Hi Matthias,

>The msdc gate is part of the MMC driver. Delete the not used code.
>
>Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
>---
> drivers/clk/mediatek/clk-mt8192-msdc.c | 21 ---------------------
> 1 file changed, 21 deletions(-)
>
>diff --git a/drivers/clk/mediatek/clk-mt8192-msdc.c b/drivers/clk/mediatek/clk-mt8192-msdc.c
>index 87c3b79b79cf..635f7a0b629a 100644
>--- a/drivers/clk/mediatek/clk-mt8192-msdc.c
>+++ b/drivers/clk/mediatek/clk-mt8192-msdc.c
>@@ -12,28 +12,15 @@
> 
> #include <dt-bindings/clock/mt8192-clk.h>
> 
>-static const struct mtk_gate_regs msdc_cg_regs = {
>-	.set_ofs = 0xb4,
>-	.clr_ofs = 0xb4,
>-	.sta_ofs = 0xb4,
>-};
>-
> static const struct mtk_gate_regs msdc_top_cg_regs = {
> 	.set_ofs = 0x0,
> 	.clr_ofs = 0x0,
> 	.sta_ofs = 0x0,
> };
> 
>-#define GATE_MSDC(_id, _name, _parent, _shift)	\
>-	GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
>-
> #define GATE_MSDC_TOP(_id, _name, _parent, _shift)	\
> 	GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
> 
>-static const struct mtk_gate msdc_clks[] = {
>-	GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22),
>-};
>-
> static const struct mtk_gate msdc_top_clks[] = {
> 	GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0),
> 	GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1),
>@@ -52,11 +39,6 @@ static const struct mtk_gate msdc_top_clks[] = {
> 	GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14),
> };
> 
>-static const struct mtk_clk_desc msdc_desc = {
>-	.clks = msdc_clks,
>-	.num_clks = ARRAY_SIZE(msdc_clks),
>-};
>-
> static const struct mtk_clk_desc msdc_top_desc = {
> 	.clks = msdc_top_clks,
> 	.num_clks = ARRAY_SIZE(msdc_top_clks),
>@@ -64,9 +46,6 @@ static const struct mtk_clk_desc msdc_top_desc = {
> 
> static const struct of_device_id of_match_clk_mt8192_msdc[] = {
> 	{
>-		.compatible = "mediatek,mt8192-msdc",
>-		.data = &msdc_desc,
>-	}, {

grep '"mediatek,mt8192-msdc"' * -RnH
arch/arm64/boot/dts/mediatek/mt8192.dtsi:868:                   compatible = "mediatek,mt8192-msdc";
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml:112:        compatible = "mediatek,mt8192-msdc";
drivers/clk/mediatek/clk-mt8192-msdc.c:67:              .compatible = "mediatek,mt8192-msdc",

I am wondering that in this case, should we have also modify the bindings document
(mediatek,mt8192-clock.yaml)?


thanks,
Miles

> 		.compatible = "mediatek,mt8192-msdc_top",
> 		.data = &msdc_top_desc,
> 	}, {
>-- 
>2.34.1

  reply	other threads:[~2022-04-25  7:31 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 14:37 matthias.bgg
2022-04-25  7:30 ` Miles Chen [this message]
2022-04-28 13:55 ` AngeloGioacchino Del Regno

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