From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A69BC433EF for ; Mon, 25 Apr 2022 16:25:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243459AbiDYQ2V (ORCPT ); Mon, 25 Apr 2022 12:28:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243473AbiDYQ1i (ORCPT ); Mon, 25 Apr 2022 12:27:38 -0400 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EFF312010E; Mon, 25 Apr 2022 09:24:34 -0700 (PDT) Received: from toolbox.int.toradex.com ([81.221.85.15]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0MhBdX-1nW2xY1deD-00MIqv; Mon, 25 Apr 2022 18:24:21 +0200 From: Marcel Ziswiler To: linux-arm-kernel@lists.infradead.org Cc: Philippe Schenker , Denys Drozdov , Andrejs Cainikovs , Marcel Ziswiler , Fabio Estevam , Frank Rowand , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team , Rob Herring , Russell King , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/14] ARM: dts: imx6ull-colibri: update usdhc1 pixmux and signaling Date: Mon, 25 Apr 2022 18:23:47 +0200 Message-Id: <20220425162356.176665-6-marcel@ziswiler.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220425162356.176665-1-marcel@ziswiler.com> References: <20220425162356.176665-1-marcel@ziswiler.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Provags-ID: V03:K1:jirVTnUYpdwujfn+5jPySQnJyzKNTOO5efbk0ZJLpEP6pqohgqi sHYfDFjcDoTJA1u4hUAYuVmoUVPn57fUKTHzXhHhvvSg29eyupyU/iNKorpjhdX1bf64h7j CvbmNw1fVgJzENnAmzhgsScpU9+M1J/ful4rmSeC266QKJ8mOtJ9F5pRn1huddCv6JtYETO 52g8VxYrqRMEJNztJawqA== X-UI-Out-Filterresults: notjunk:1;V03:K0:jjpJSo0kxAw=:t4G94iIIJlDsY6gGkRrKYU fv6j2xmquzS7UANO8Awelm41xEicz+jG2/1fLyhG4/jDNqHGmpjSasMas0ry/AMm6MD9xtf47 eAVRSkG3FxVPwE9s+0FciWSOZap1dbcwKOlhN1/Tg8+IQP17XmT4RBW3X177gUcxupdBZ7dCH w8DjMSDVKgZLVsOaJmWLJrl7cEVW2LpZ1qQIrnRz4gntmbyfdmcBr3Tu6vT5nUJNom+jPsL3S XnT7Bg3d2Yy9bYtKPCMvLGNqVKb0Ua7NfWvnvr/cFTh0wFi7YEYyCdkNDIzUTYbbcloq4BFSS tdkiDcPPkvJBVrdtOLcVBf2hvkh7/zklSHKdcFt+HNyzkLU2+Tc1aG/DD8H2jqUgpuUsSNbeU ekF8S4yW+h40wgjMrcf6UQN5ZoosYRiF/MTpkcNt81MSpJ4XiKU4AQ0fjhStX/9xFgW1haFM4 DFQoEEh7h/Bd9vDUIvZHcFHWL+cmvXn3qxlfjo2rWJb0AVERQaNgBqeZjRVTWI/bmjAuaT9bk VhwjbWJ9ovnavuyG+ZJF5lr3FDLCiFA8ihafzYrHOZYd/nT9KDXSvunjC87STDzByOE0UMezD j3oS/ena42PNmDiQZVEtjsLbfWA8d5/lrZ6ubw4ubT5DZ78Kfrddjp4N3VbCuPD8NVxswYHAS e9wwAKHqEGmq9S7a25MmVy6RDIql37CmWswhKrS7QcoylDEpMU+iVoY3StV8517FGY/fOvTr3 KWhPHIBNRXLxtZTY Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Philippe Schenker Due to many carrier boards pulling the usdhc1 signals up to 3.3 volt we need to disable 1.8 volt signaling. Adding the no-1-8-v property basically disables UHS-I modes by default. Also pull-up the command and data lines to the +V3.3_1.8_SD rail and set them to the 200 MHz speed grade (e.g. pinmux bits 7-6: meaning 11 SPEED_3_max_200MHz). Explicitly specify a bus-width of <4> in the module-level device tree include file and drop the no-1-8-v property from the carrier boards device trees. Signed-off-by: Philippe Schenker Signed-off-by: Denys Drozdov Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler --- (no changes since v1) .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 14 -------- arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++------- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index a78849fd2afa..ea086b305d22 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -159,20 +159,6 @@ &usbotg2 { }; &usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - disable-wp; - wakeup-source; - keep-power-in-suspend; vmmc-supply = <®_3v3>; - vqmmc-supply = <®_sd1_vmmc>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 8b5cbe9132a2..bd8736d90cbb 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -35,7 +35,7 @@ reg_module_3v3_avdd: regulator-module-3v3-avdd { regulator-max-microvolt = <3300000>; }; - reg_sd1_vmmc: regulator-sd1-vmmc { + reg_sd1_vqmmc: regulator-sd1-vqmmc { compatible = "regulator-gpio"; gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -232,9 +232,21 @@ &usbotg2 { }; &usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; + bus-width = <4>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + disable-wp; + keep-power-in-suspend; + no-1-8-v; + vqmmc-supply = <®_sd1_vqmmc>; + wakeup-source; }; &wdog1 { @@ -550,8 +562,8 @@ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */ pinctrl_usdhc1: usdhc1-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */ - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */ + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ @@ -561,8 +573,8 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 @@ -572,12 +584,12 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; @@ -588,7 +600,7 @@ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 >; -- 2.35.1