From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEF04C433EF for ; Tue, 26 Apr 2022 13:27:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350972AbiDZNay (ORCPT ); Tue, 26 Apr 2022 09:30:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238485AbiDZNaw (ORCPT ); Tue, 26 Apr 2022 09:30:52 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A275118D6A3 for ; Tue, 26 Apr 2022 06:27:44 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 70818ED1; Tue, 26 Apr 2022 06:27:44 -0700 (PDT) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E4F5D3F774; Tue, 26 Apr 2022 06:27:42 -0700 (PDT) Date: Tue, 26 Apr 2022 14:27:40 +0100 From: Sudeep Holla To: =?utf-8?B?546L5pOO?= Cc: Catalin Marinas , Sudeep Holla , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "vincent.guittot@linaro.org" , "dietmar.eggemann@arm.com" , Jonathan Cameron Subject: Re: [PATCH V2 0/2] Add complex scheduler level for arm64 Message-ID: <20220426132740.yhthgoazoolvlven@bogus> References: <1650628289-67716-1-git-send-email-wangqing@vivo.com> <20220425141926.00004d2e@Huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 26, 2022 at 07:05:15AM +0000, 王擎 wrote: > > Hi Sudeep: > > I am thinking if it is possible to add a complex level cpu topology > between cluster and SMT? > > We can describe it directly in “cpu-map”, instead of parsing it through > the cache info. > I don't know or understand what you mean by that. Do you have a proposal for DT bindings ? Please post the patch with details on the motivation for the change to help us understand your proposal. I can't comment much without seeing or understanding your proposal at this moment. -- Regards, Sudeep