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Fri, 29 Apr 2022 04:34:57 -0700 From: Ashish Mhetre To: , , , , , , , , , CC: , , Ashish Mhetre Subject: [Patch v10 3/4] dt-bindings: memory: tegra: Update validation for reg and reg-names Date: Fri, 29 Apr 2022 17:04:37 +0530 Message-ID: <20220429113438.13988-4-amhetre@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220429113438.13988-1-amhetre@nvidia.com> References: <20220429113438.13988-1-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0318f71f-72c3-41a3-70f7-08da29d44e2b X-MS-TrafficTypeDiagnostic: MWHPR12MB1280:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GlOVTtsbYimHJdFiB/6OWqGCu6os/EFoqmy42L/fwRUatZgcO/DlZjcTcs3KGyN+Dtf0/wDKyr3vK0Rqp9f94fS0UIsGnmC3u7w5FOgFmabSCqvTcJgAy1E1UuTHS9oNODAURJZzejBPAoC8j9LRXyvLvY9YiyElTPCbdkcmiNC5WY7G9qZEOJgidKPa6lTCj5Lv4d5Emx0hXzjRRLdR6Bej5mg1cUKt2iDfVzKXbRLxxkSfJjwylk5uUC+yaXW7z9falxAYlAwdfB1BgJE22xXmMZlqNckXDz4v0N5uyVr12F7hArrGcBvPIk+GtheQTxqVrLJ4vn2R1USr6zQza8ixTMfLQxBh6suWQSjPec5eXAIuD84xZ0tzRiMgY51J0hG4V4xfv3/1blFotuwnScUFKqtSzI0mQXYvs4QEgbkC5wRYBfp4AyYhiD921h6gGhzOqbSJF7T4yPq504Y+Oag2ff0orSwLdWg+T/KwZl62wGAdCYtMMdfUXzGw3YmFq1NsTkcC6f5UX0YrtO9Yf7GJHUlpRUi4XM5ROq4yt7KeLAsLWIuwrqWC4v1bPMUJ1glJy+FlTO46mhql953Su52yO+R7slzVvzse3SkpSCV98mu4QjVz+LUuyUKsRyoh5eDApIzmXw/ZdpXFrr3swkbjz74TBlE2CYeTEJt2URfdrSTTW/11d/ZBcTBHHibiybFZb69tV5GEIAjHnrZK5cpUx+VKLF/eLi32FyeYOi8= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(5660300002)(81166007)(82310400005)(107886003)(316002)(8936002)(426003)(2616005)(47076005)(36860700001)(26005)(70586007)(70206006)(83380400001)(508600001)(336012)(110136005)(36756003)(1076003)(15650500001)(4326008)(8676002)(6666004)(40460700003)(186003)(921005)(356005)(86362001)(7696005)(2906002)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2022 11:35:04.6059 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0318f71f-72c3-41a3-70f7-08da29d44e2b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1280 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each. There is 1 reg item for memory controller stream-id registers. So update the reg minItems and maxItems accordingly in tegra186 devicetree documentation. Also update validation for reg-names added for these corresponding reg items. ABI change due to new bindings is intended but backward compatibility is preserved in driver. Reviewed-by: Rob Herring Signed-off-by: Ashish Mhetre --- .../nvidia,tegra186-mc.yaml | 80 +++++++++++++++++-- 1 file changed, 74 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 13c4c82fd0d3..c7cfa6c2cd81 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -34,8 +34,12 @@ properties: - nvidia,tegra234-mc reg: - minItems: 1 - maxItems: 3 + minItems: 6 + maxItems: 18 + + reg-names: + minItems: 6 + maxItems: 18 interrupts: items: @@ -142,7 +146,18 @@ allOf: then: properties: reg: - maxItems: 1 + maxItems: 6 + description: 5 memory controller channels and 1 for stream-id registers + + reg-names: + maxItems: 6 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 - if: properties: @@ -151,7 +166,30 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 - if: properties: @@ -160,13 +198,37 @@ allOf: then: properties: reg: - minItems: 3 + minItems: 18 + description: 17 memory controller channels and 1 for stream-id registers + + reg-names: + minItems: 18 + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 additionalProperties: false required: - compatible - reg + - reg-names - interrupts - "#address-cells" - "#size-cells" @@ -182,7 +244,13 @@ examples: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = ; #address-cells = <2>; -- 2.17.1