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Fri, 29 Apr 2022 04:35:02 -0700 From: Ashish Mhetre To: , , , , , , , , , CC: , , Ashish Mhetre Subject: [Patch v10 4/4] arm64: tegra: Add memory controller channels Date: Fri, 29 Apr 2022 17:04:38 +0530 Message-ID: <20220429113438.13988-5-amhetre@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220429113438.13988-1-amhetre@nvidia.com> References: <20220429113438.13988-1-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 67f8fd5d-7060-48fe-265c-08da29d4511c X-MS-TrafficTypeDiagnostic: BL1PR12MB5729:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bHvso1OeheVpd5xPBKwsSc2SOeKMg3J3GAfDdWMh8hf8yfNgeGbciydxiSbubCpcTvjTiATMpNPWOEHY9H7Y0hEQpQJcabqugqLPEFyuW4l+5E2Go7eTc4sVUznvTwdgQ9SGhZYCkLrPgtVD0PyhdtL52QN5WP+IUmudDvKgL7kmktcMEy3N8IRch+7jCciuZAKPG8GJBCnBbKQ/uMT8QQ1qYsh+mYsRcA9v7TuNy7dxlocJLpp65fpY1sE24k0M0mmEZQMTfzVLJDAgoAXIP6Syh+vzCz/+Znd4iSNgWfZcDGc8Vx8gJlgQOMaoQ1dAPZ5iZMr0KPNG6OhO+ytiPsOpN3H5jzvDcTzWI3DMLLeNbld0ce1huP/KZ2ig/ikVjC8Use4GATo+brHRW4rPsui8wvbHnHLlj2Av1OphssM1g8jknT+pTsPEBgSyzlfx5VDq61bPGid4zZStcckaN5d1IolyedZfts00Ceey3yfZ/DPM9213xgH2iW3oWNBzzjNZ6JTwFeX6Yz/lDAI1E0YmXnqtcwgN3gAyq0/NdwM7Ix1WEjk9bc1g3ks53Vbrgn3exqAUhM06JiFhBYuqNDcrmbW6z9QPL5Dmwk3K0HUgNieXFaXP3oFBy7pwrBleetvUHow+/dcIYNNkXjyo8hx5kchSYc2E6vtLd/bZam7lfXpwNXwW4EjZNxOh8Rn6lFUQxZf3rxVkwa9bkipXXISba25jZJ9mA4huliDUI/w= X-Forefront-Antispam-Report: CIP:12.22.5.234;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(86362001)(81166007)(508600001)(8676002)(54906003)(82310400005)(110136005)(7696005)(36860700001)(316002)(36756003)(70586007)(4326008)(70206006)(2906002)(26005)(186003)(5660300002)(1076003)(6666004)(40460700003)(426003)(47076005)(336012)(921005)(356005)(8936002)(83380400001)(2616005)(107886003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2022 11:35:09.5857 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67f8fd5d-7060-48fe-265c-08da29d4511c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5729 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org >From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping. Signed-off-by: Ashish Mhetre --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24 +++++++++++++++++++++--- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 +++++++++++++++++++++--- 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 2e7faa1e0b9c..0e9afc3e2f26 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -528,7 +528,13 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = ; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f9d343b24597..d1f8248c00f4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -612,9 +612,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", + "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = ; #interconnect-cells = <1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 71c21d7d0551..cb3af539e477 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -515,9 +515,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", + "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = ; #interconnect-cells = <1>; status = "okay"; -- 2.17.1