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From: Oliver Upton <oupton@google.com>
To: kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, maz@kernel.org,
	james.morse@arm.com, alexandru.elisei@arm.com,
	suzuki.poulose@arm.com, reijiw@google.com, ricarkol@google.com,
	Oliver Upton <oupton@google.com>
Subject: [PATCH v4 7/7] Revert "KVM/arm64: Don't emulate a PMU for 32-bit guests if feature not set"
Date: Tue,  3 May 2022 06:02:05 +0000	[thread overview]
Message-ID: <20220503060205.2823727-8-oupton@google.com> (raw)
In-Reply-To: <20220503060205.2823727-1-oupton@google.com>

This reverts commit 8f6379e207e7d834065a080f407a60d67349d961.

The original change was not problematic but chose nonarchitected PMU
register behavior over a NULL deref as KVM failed to hide the PMU in the
ID_DFR0.

Since KVM now provides a sane value for ID_DFR0 and UNDEFs the guest for
unsupported accesses, drop the unneeded checks in PMU register handlers.

Signed-off-by: Oliver Upton <oupton@google.com>
---
 arch/arm64/kvm/pmu-emul.c | 23 +----------------------
 1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
index 3dc990ac4f44..78fdc443adc7 100644
--- a/arch/arm64/kvm/pmu-emul.c
+++ b/arch/arm64/kvm/pmu-emul.c
@@ -177,9 +177,6 @@ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
 	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	struct kvm_pmc *pmc = &pmu->pmc[select_idx];
 
-	if (!kvm_vcpu_has_pmu(vcpu))
-		return 0;
-
 	counter = kvm_pmu_get_pair_counter_value(vcpu, pmc);
 
 	if (kvm_pmu_pmc_is_chained(pmc) &&
@@ -201,9 +198,6 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
 {
 	u64 reg;
 
-	if (!kvm_vcpu_has_pmu(vcpu))
-		return;
-
 	reg = (select_idx == ARMV8_PMU_CYCLE_IDX)
 	      ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
 	__vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx);
@@ -328,9 +322,6 @@ void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
 	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	struct kvm_pmc *pmc;
 
-	if (!kvm_vcpu_has_pmu(vcpu))
-		return;
-
 	if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val)
 		return;
 
@@ -366,7 +357,7 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
 	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	struct kvm_pmc *pmc;
 
-	if (!kvm_vcpu_has_pmu(vcpu) || !val)
+	if (!val)
 		return;
 
 	for (i = 0; i < ARMV8_PMU_MAX_COUNTERS; i++) {
@@ -536,9 +527,6 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
 	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	int i;
 
-	if (!kvm_vcpu_has_pmu(vcpu))
-		return;
-
 	if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))
 		return;
 
@@ -588,9 +576,6 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val)
 {
 	int i;
 
-	if (!kvm_vcpu_has_pmu(vcpu))
-		return;
-
 	if (val & ARMV8_PMU_PMCR_E) {
 		kvm_pmu_enable_counter_mask(vcpu,
 		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0));
@@ -754,9 +739,6 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
 {
 	u64 reg, mask;
 
-	if (!kvm_vcpu_has_pmu(vcpu))
-		return;
-
 	mask  =  ARMV8_PMU_EVTYPE_MASK;
 	mask &= ~ARMV8_PMU_EVTYPE_EVENT;
 	mask |= kvm_pmu_event_mask(vcpu->kvm);
@@ -845,9 +827,6 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
 	u64 val, mask = 0;
 	int base, i, nr_events;
 
-	if (!kvm_vcpu_has_pmu(vcpu))
-		return 0;
-
 	if (!pmceid1) {
 		val = read_sysreg(pmceid0_el0);
 		base = 0;
-- 
2.36.0.464.gb9c8b46e94-goog


  parent reply	other threads:[~2022-05-03  6:02 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03  6:01 [PATCH v4 0/7] KVM: arm64: Limit feature register reads from AArch32 Oliver Upton
2022-05-03  6:01 ` [PATCH v4 1/7] KVM: arm64: Return a bool from emulate_cp() Oliver Upton
2022-05-03  6:02 ` [PATCH v4 2/7] KVM: arm64: Don't write to Rt unless sys_reg emulation succeeds Oliver Upton
2022-05-03  6:02 ` [PATCH v4 3/7] KVM: arm64: Wire up CP15 feature registers to their AArch64 equivalents Oliver Upton
2022-05-03  6:02 ` [PATCH v4 4/7] KVM: arm64: Plumb cp10 ID traps through the AArch64 sysreg handler Oliver Upton
2022-05-03  6:02 ` [PATCH v4 5/7] KVM: arm64: Start trapping ID registers for 32 bit guests Oliver Upton
2022-05-03  6:02 ` [PATCH v4 6/7] KVM/arm64: Hide AArch32 PMU registers when not available Oliver Upton
2022-05-03  6:02 ` Oliver Upton [this message]
2022-05-03 10:31 ` [PATCH v4 0/7] KVM: arm64: Limit feature register reads from AArch32 Marc Zyngier

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