From: Sascha Hauer <s.hauer@pengutronix.de>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com,
shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org,
perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ASoC: fsl_micfil: fix the naming style for mask definition
Date: Thu, 5 May 2022 09:50:17 +0200 [thread overview]
Message-ID: <20220505075017.GJ4012@pengutronix.de> (raw)
In-Reply-To: <1651736047-28809-1-git-send-email-shengjiu.wang@nxp.com>
On Thu, May 05, 2022 at 03:34:07PM +0800, Shengjiu Wang wrote:
> Remove the _SHIFT for the mask definition.
>
> Fixes: 17f2142bae4b ("ASoC: fsl_micfil: use GENMASK to define register bit fields")
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha
> sound/soc/fsl/fsl_micfil.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
> index 08901827047d..053caba3caf3 100644
> --- a/sound/soc/fsl/fsl_micfil.h
> +++ b/sound/soc/fsl/fsl_micfil.h
> @@ -74,9 +74,9 @@
> #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
>
> /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
> -#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
> -#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16)
> -#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
> +#define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24)
> +#define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16)
> +#define MICFIL_VAD0_CTRL1_INITT GENMASK(12, 8)
> #define MICFIL_VAD0_CTRL1_ST10 BIT(4)
> #define MICFIL_VAD0_CTRL1_ERIE BIT(3)
> #define MICFIL_VAD0_CTRL1_IE BIT(2)
> @@ -106,7 +106,7 @@
>
> /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
> #define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
> -#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8)
> +#define MICFIL_VAD0_ZCD_ZCDADJ GENMASK(11, 8)
> #define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
> #define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
> #define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
> --
> 2.17.1
>
>
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next prev parent reply other threads:[~2022-05-05 7:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 7:34 Shengjiu Wang
2022-05-05 7:50 ` Sascha Hauer [this message]
2022-05-05 15:12 ` Mark Brown
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