From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E052FC4332F for ; Thu, 5 May 2022 13:43:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379919AbiEENrH (ORCPT ); Thu, 5 May 2022 09:47:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379889AbiEENrE (ORCPT ); Thu, 5 May 2022 09:47:04 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD87457981; Thu, 5 May 2022 06:43:16 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 245Dh7Ka039902; Thu, 5 May 2022 08:43:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1651758188; bh=dwDqfTZcpar8twstwU6LFYm3Ok1etJ+eeBYha6p9PDI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mtdibd95XMmviVydRH85Yc7rRHWpYYoi3nIXqgbN2vdjXCOuBG/j2TG9f3rrXakut BW53JTiuQykX1RIkBoB8hABOGEDZygRM6Pf1BkEiEn1kvKd4qyw3vbkqPius2Nqblu qdPchkdehcd8guD3K3U+MeHac5AFOz7Ip0BoUaG0= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 245Dh7bB053435 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 May 2022 08:43:07 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 5 May 2022 08:43:07 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 5 May 2022 08:43:06 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 245Dh6mQ077914; Thu, 5 May 2022 08:43:06 -0500 From: Aradhya Bhatia To: Vignesh Raghavendra CC: Nishanth Menon , Rob Herring , Linux ARM Kernel List , Devicetree List , Linux Kernel List , Aradhya Bhatia , Rahul T R Subject: [PATCH v2 1/4] arm64: dts: ti: k3-am62-main: Add node for Display SubSystem Date: Thu, 5 May 2022 19:13:00 +0530 Message-ID: <20220505134303.23208-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505134303.23208-1-a-bhatia1@ti.com> References: <20220505134303.23208-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT node for the Display SubSystem on the am62x soc in cbass_main. The DSS IP on this soc is compatible with the one on the am65x soc. The DSS supports one each of video pipeline (vid) and video-lite pipeline (vidl1). It outputs OLDI signals on one video port (vp1) and DPI signals on another (vp2). The video ports are connected to the pipelines via 2 identical overlay managers (ovr1 and ovr2). Signed-off-by: Aradhya Bhatia Reviewed-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index eec8dae65e7c..ff21efa4ffad 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -515,6 +515,36 @@ cpts@3d000 { }; }; + dss: dss@30200000 { + compatible = "ti,am65x-dss"; + + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + + clocks = <&k3_clks 186 4>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + + clock-names = "fck", "vp1", "vp2"; + + interrupts = ; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; -- 2.36.0