From: Peter Zijlstra <peterz@infradead.org>
To: x86@kernel.org, kan.liang@linux.intel.com, eranian@google.com
Cc: linux-kernel@vger.kernel.org, peterz@infradead.org,
acme@kernel.org, mark.rutland@arm.com,
alexander.shishkin@linux.intel.com, jolsa@kernel.org,
namhyung@kernel.org
Subject: [PATCH 2/5] perf/x86: Add two more x86_pmu methods
Date: Wed, 11 May 2022 16:20:39 +0200 [thread overview]
Message-ID: <20220511142345.146224050@infradead.org> (raw)
In-Reply-To: <20220511142037.353492804@infradead.org>
In order to clean up x86_perf_event_{set_period,update)() start by
adding them as x86_pmu methods.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
arch/x86/events/core.c | 22 +++++++++++++++++-----
arch/x86/events/perf_event.h | 5 +++++
2 files changed, 22 insertions(+), 5 deletions(-)
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -72,6 +72,9 @@ DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x
DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
+DEFINE_STATIC_CALL_NULL(x86_pmu_set_period, *x86_pmu.set_period);
+DEFINE_STATIC_CALL_NULL(x86_pmu_update, *x86_pmu.update);
+
DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
@@ -1518,7 +1521,7 @@ static void x86_pmu_start(struct perf_ev
if (flags & PERF_EF_RELOAD) {
WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
- x86_perf_event_set_period(event);
+ static_call(x86_pmu_set_period)(event);
}
event->hw.state = 0;
@@ -1610,7 +1613,7 @@ void x86_pmu_stop(struct perf_event *eve
* Drain the remaining delta count out of a event
* that we are disabling:
*/
- x86_perf_event_update(event);
+ static_call(x86_pmu_update)(event);
hwc->state |= PERF_HES_UPTODATE;
}
}
@@ -1700,7 +1703,7 @@ int x86_pmu_handle_irq(struct pt_regs *r
event = cpuc->events[idx];
- val = x86_perf_event_update(event);
+ val = static_call(x86_pmu_update)(event);
if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
continue;
@@ -1709,7 +1712,7 @@ int x86_pmu_handle_irq(struct pt_regs *r
*/
handled++;
- if (!x86_perf_event_set_period(event))
+ if (!static_call(x86_pmu_set_period)(event))
continue;
perf_sample_data_init(&data, 0, event->hw.last_period);
@@ -2023,6 +2026,9 @@ static void x86_pmu_static_call_update(v
static_call_update(x86_pmu_del, x86_pmu.del);
static_call_update(x86_pmu_read, x86_pmu.read);
+ static_call_update(x86_pmu_set_period, x86_pmu.set_period);
+ static_call_update(x86_pmu_update, x86_pmu.update);
+
static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
@@ -2042,7 +2048,7 @@ static void x86_pmu_static_call_update(v
static void _x86_pmu_read(struct perf_event *event)
{
- x86_perf_event_update(event);
+ static_call(x86_pmu_update)(event);
}
void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
@@ -2148,6 +2154,12 @@ static int __init init_hw_perf_events(vo
if (!x86_pmu.guest_get_msrs)
x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
+ if (!x86_pmu.set_period)
+ x86_pmu.set_period = x86_perf_event_set_period;
+
+ if (!x86_pmu.update)
+ x86_pmu.update = x86_perf_event_update;
+
x86_pmu_static_call_update();
/*
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -735,6 +735,8 @@ struct x86_pmu {
void (*add)(struct perf_event *);
void (*del)(struct perf_event *);
void (*read)(struct perf_event *event);
+ int (*set_period)(struct perf_event *event);
+ u64 (*update)(struct perf_event *event);
int (*hw_config)(struct perf_event *event);
int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
unsigned eventsel;
@@ -1031,6 +1033,9 @@ static struct perf_pmu_format_hybrid_att
struct pmu *x86_get_pmu(unsigned int cpu);
extern struct x86_pmu x86_pmu __read_mostly;
+DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period);
+DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update);
+
static __always_inline struct x86_perf_task_context_opt *task_context_opt(void *ctx)
{
if (static_cpu_has(X86_FEATURE_ARCH_LBR))
next prev parent reply other threads:[~2022-05-11 14:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-11 14:20 [PATCH 0/5] perf/x86: Some cleanups Peter Zijlstra
2022-05-11 14:20 ` [PATCH 1/5] perf/x86/amd: Fix AMD BRS period adjustment Peter Zijlstra
2022-05-11 14:20 ` Peter Zijlstra [this message]
2022-05-11 14:20 ` [PATCH 3/5] perf/x86/intel: Move the topdown stuff into the intel driver Peter Zijlstra
2022-05-11 14:20 ` [PATCH 4/5] perf/x86: Change x86_pmu::limit_period signature Peter Zijlstra
2022-05-11 17:47 ` Liang, Kan
2022-05-11 20:06 ` Peter Zijlstra
2022-05-11 14:20 ` [PATCH 5/5] perf/x86: Add a x86_pmu::limit_period static_call Peter Zijlstra
2022-05-11 15:34 ` [RFC][PATCH 6/5] perf/x86/intel: Remove x86_pmu::set_topdown_event_period Peter Zijlstra
2022-05-11 15:35 ` [RFC][PATCH 7/5] perf/x86/intel: Remove x86_pmu::update_topdown_event Peter Zijlstra
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