From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 496C7C433F5 for ; Fri, 13 May 2022 18:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383504AbiEMS6P (ORCPT ); Fri, 13 May 2022 14:58:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383484AbiEMS6E (ORCPT ); Fri, 13 May 2022 14:58:04 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 506A76BFD3 for ; Fri, 13 May 2022 11:58:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652468283; x=1684004283; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=rCKiBLo5JPRevaGfzEi2/7NKS4ODTjaZmZIfll5payA=; b=bzXOv8Ur/Dyf8IXM97WGcM9FqyG5GYI/5yKQLxTPRg1MyXvYEDYjJNle GoN3oq+HczowEHatVndBVNgBOntiLZSvquPTV8/3Mut8GSfrnHpjsI70u aRe9WuWThsbVxdBv/ACmhIH+PoE3IxRFuL2tT79rSbnLnK7mzVwB5ytz7 eAArfZMO3EpXxVUq+q0rJLtjL987Y6N1nB0hcxsGVqE0o4mqlqY22ffuf LOdN8l8cIeZK3G4npHuVaqZRsK7VdtuLom1wSMrDVU5YJmsx8gXs46pym lSvfLsrB8C6qDHBCg4naPPljwWsN5x+SEZmIBxnaVTfTxw4wnWBcvUT8H Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10346"; a="295647410" X-IronPort-AV: E=Sophos;i="5.91,223,1647327600"; d="scan'208";a="295647410" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2022 11:58:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,223,1647327600"; d="scan'208";a="521535494" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga003.jf.intel.com with ESMTP; 13 May 2022 11:58:02 -0700 Date: Fri, 13 May 2022 12:01:37 -0700 From: Ricardo Neri To: Thomas Gleixner Cc: x86@kernel.org, Tony Luck , Andi Kleen , Stephane Eranian , Andrew Morton , Joerg Roedel , Suravee Suthikulpanit , David Woodhouse , Lu Baolu , Nicholas Piggin , "Ravi V. Shankar" , Ricardo Neri , iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 12/29] iommu/amd: Enable NMIPass when allocating an NMI irq Message-ID: <20220513190137.GC22683@ranerica-svr.sc.intel.com> References: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com> <20220506000008.30892-13-ricardo.neri-calderon@linux.intel.com> <87tua2fj41.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87tua2fj41.ffs@tglx> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 06, 2022 at 11:26:22PM +0200, Thomas Gleixner wrote: > On Thu, May 05 2022 at 16:59, Ricardo Neri wrote: > > > > + if (info->flags & X86_IRQ_ALLOC_AS_NMI) { > > + /* Only one IRQ per NMI */ > > + if (nr_irqs != 1) > > + return -EINVAL; > > See previous reply. I remove this check. Thanks and BR, Ricardo >