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Peter Anvin" Subject: [PATCH V2 5/7] x86/entry: Add the C verion of SWITCH_TO_KERNEL_CR3 as switch_to_kernel_cr3() Date: Mon, 16 May 2022 21:17:36 +0800 Message-Id: <20220516131739.521817-6-jiangshanlai@gmail.com> X-Mailer: git-send-email 2.19.1.6.gb485710b In-Reply-To: <20220516131739.521817-1-jiangshanlai@gmail.com> References: <20220516131739.521817-1-jiangshanlai@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lai Jiangshan Add the C version switch_to_kernel_cr3() which implements the macro SWITCH_TO_KERNEL_CR3() in arch/x86/entry/calling.h. No functional difference intended. Note: The compiler generates "AND $0xe7,%ah" (3 bytes) for the code "cr3 = user_cr3 & ~PTI_USER_PGTABLE_AND_PCID_MASK" while the ASM code in SWITCH_TO_KERNEL_CR3() results "AND $0xffffffffffffe7ff,%rax" (6 bytes). The compiler generates lengthier code for "cr3 |= X86_CR3_PCID_NOFLUSH" because it uses "MOVABS+OR" (13 bytes) rather than a single "BTS" (5 bytes). Signed-off-by: Lai Jiangshan --- arch/x86/entry/entry64.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/x86/entry/entry64.c b/arch/x86/entry/entry64.c index ace73861c2a0..bd77cc8373ce 100644 --- a/arch/x86/entry/entry64.c +++ b/arch/x86/entry/entry64.c @@ -12,3 +12,27 @@ * is the PTI user CR3 or both. */ #include + +#ifdef CONFIG_PAGE_TABLE_ISOLATION +static __always_inline void pti_switch_to_kernel_cr3(unsigned long user_cr3) +{ + /* + * Clear PCID and "PAGE_TABLE_ISOLATION bit", point CR3 + * at kernel pagetables: + */ + unsigned long cr3 = user_cr3 & ~PTI_USER_PGTABLE_AND_PCID_MASK; + + if (static_cpu_has(X86_FEATURE_PCID)) + cr3 |= X86_CR3_PCID_NOFLUSH; + + native_write_cr3(cr3); +} + +static __always_inline void switch_to_kernel_cr3(void) +{ + if (static_cpu_has(X86_FEATURE_PTI)) + pti_switch_to_kernel_cr3(__native_read_cr3()); +} +#else +static __always_inline void switch_to_kernel_cr3(void) {} +#endif -- 2.19.1.6.gb485710b