From: Sandipan Das <sandipan.das@amd.com>
To: <linux-kernel@vger.kernel.org>,
<linux-perf-users@vger.kernel.org>, <x86@kernel.org>
Cc: <peterz@infradead.org>, <bp@alien8.de>, <acme@kernel.org>,
<namhyung@kernel.org>, <jolsa@kernel.org>, <tglx@linutronix.de>,
<mingo@redhat.com>, <pbonzini@redhat.com>, <jmattson@google.com>,
<like.xu.linux@gmail.com>, <eranian@google.com>,
<jroedel@suse.de>, <ananth.narayan@amd.com>,
<ravi.bangoria@amd.com>, <santosh.shukla@amd.com>,
<sandipan.das@amd.com>
Subject: [PATCH] perf/x86/amd/core: Fix reloading events for SVM
Date: Wed, 18 May 2022 14:13:27 +0530 [thread overview]
Message-ID: <20220518084327.464005-1-sandipan.das@amd.com> (raw)
Commit 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only
counting with SVM disabled") addresses an issue in which the
Host-Only bit in the counter control registers needs to be
masked off when SVM is not enabled.
The events need to be reloaded whenever SVM is enabled or
disabled for a CPU and this requires the PERF_CTL registers
to be reprogrammed using {enable,disable}_all(). However,
PerfMonV2 variants of these functions do not reprogram the
PERF_CTL registers. Hence, the legacy enable_all() function
should also be called.
Fixes: 9622e67e3980 ("perf/x86/amd/core: Add PerfMonV2 counter control")
Reported-by: Like Xu <likexu@tencent.com>
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
---
arch/x86/events/amd/core.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 359d575c27e2..37b175870ee8 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -1467,6 +1467,24 @@ __init int amd_pmu_init(void)
return 0;
}
+static inline void amd_pmu_reload_virt(void)
+{
+ if (x86_pmu.version >= 2) {
+ /*
+ * Clear global enable bits, reprogram the PERF_CTL
+ * registers with updated perf_ctr_virt_mask and then
+ * set global enable bits once again
+ */
+ amd_pmu_v2_disable_all();
+ amd_pmu_enable_all(0);
+ amd_pmu_v2_enable_all(0);
+ return;
+ }
+
+ amd_pmu_disable_all();
+ amd_pmu_enable_all(0);
+}
+
void amd_pmu_enable_virt(void)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
@@ -1474,8 +1492,7 @@ void amd_pmu_enable_virt(void)
cpuc->perf_ctr_virt_mask = 0;
/* Reload all events */
- amd_pmu_disable_all();
- x86_pmu_enable_all(0);
+ amd_pmu_reload_virt();
}
EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);
@@ -1492,7 +1509,6 @@ void amd_pmu_disable_virt(void)
cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
/* Reload all events */
- amd_pmu_disable_all();
- x86_pmu_enable_all(0);
+ amd_pmu_reload_virt();
}
EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);
--
2.34.1
next reply other threads:[~2022-05-18 8:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-18 8:43 Sandipan Das [this message]
2022-05-19 21:56 ` [tip: perf/core] " tip-bot2 for Sandipan Das
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