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From: Miles Chen <miles.chen@mediatek.com>
To: <yassine.oudjana@gmail.com>
Cc: <angelogioacchino.delregno@collabora.com>,
	<bgolaszewski@baylibre.com>, <chun-jie.chen@mediatek.com>,
	<devicetree@vger.kernel.org>, <ikjn@chromium.org>,
	<krzysztof.kozlowski+dt@linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <matthias.bgg@gmail.com>,
	<miles.chen@mediatek.com>, <mturquette@baylibre.com>,
	<p.zabel@pengutronix.de>, <robh+dt@kernel.org>,
	<sam.shih@mediatek.com>, <sboyd@kernel.org>,
	<tinghan.shen@mediatek.com>, <weiyi.lu@mediatek.com>,
	<wenst@chromium.org>, <y.oudjana@protonmail.com>,
	<~postmarketos/upstreaming@lists.sr.ht>
Subject: Re: [PATCH v2 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock drivers
Date: Fri, 20 May 2022 17:35:01 +0800	[thread overview]
Message-ID: <20220520093501.28758-1-miles.chen@mediatek.com> (raw)
In-Reply-To: <NJC6CR.M4CF312LSXXV1@gmail.com>


>> 
>> Thanks for submitting this patch.
>> 
>> I compare this with drivers/clk/mediatek/clk-mt7986-apmixed.c,
>> and other clk files are using macros to make the mtk_pll_data array
>> more readable.
>
>I'd actually argue that macros make it less readable. While reading
>other drivers I had a lot of trouble figuring out which argument
>is which field of the struct, and had to constantly go back to the
>macro definitions and count arguments to find it. Having it this
>way, each value is labeled clearly with the field it's in. I think
>the tradeoff between line count and readability here is worth it.

It is easier for multiple developers to work together if we have a common style.

How do you think?

Thanks,
Miles

>
>> 
>> Would you mind following the same style for all c files, please?
>> 
>> e.g.,
>> 	static const struct mtk_pll_data plls[] = {
>> 		PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
>> 				0x0200, 4, 0, 0x0204, 0),
>> 		PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 
>> 32,
>> 				0x0210, 4, 0, 0x0214, 0),
>> 		...
>> 	};
>> 
>>>  +	},
>>>  +		.reg = APLL1_CON0,
>>>  +		.pwr_reg = APLL1_PWR_CON0,
>>>  +module_platform_driver(clk_mt6735_apmixedsys);
>>>  +
>>>  +MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
>>>  +MODULE_DESCRIPTION("Mediatek MT6735 apmixedsys clock driver");
>> 
>> Would you mind changing all Mediatek to MediaTek?
>> i.e.,
>> 
>> s/Mediatek/MediaTek/
>> 
>
>Sure. Will fix it.

thanks
>
>> 
>> thanks,
>> Miles
>>  +MODULE_LICENSE("GPL");
>> 
>
>Thanks,
>Yassine
>
>
>
>

  reply	other threads:[~2022-05-20  9:35 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-19 14:22 [PATCH v2 0/4] Mediatek MT6735 main clock and reset drivers Yassine Oudjana
2022-05-19 14:22 ` [PATCH v2 1/4] dt-bindings: clock: Add Mediatek MT6735 clock bindings Yassine Oudjana
2022-05-19 14:22 ` [PATCH v2 2/4] dt-bindings: reset: Add MT6735 reset bindings Yassine Oudjana
2022-05-20  8:55   ` AngeloGioacchino Del Regno
2022-05-20  9:13     ` Yassine Oudjana
2022-05-23 12:15       ` AngeloGioacchino Del Regno
2022-05-19 14:22 ` [PATCH v2 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Yassine Oudjana
2022-05-19 14:22 ` [PATCH v2 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock drivers Yassine Oudjana
2022-05-20  8:35   ` Miles Chen
2022-05-20  9:18     ` Yassine Oudjana
2022-05-20  9:35       ` Miles Chen [this message]
2022-05-20 10:26         ` AngeloGioacchino Del Regno
2022-05-20 11:08           ` Yassine Oudjana
2022-05-22 17:02           ` Miles Chen
2022-08-13 10:44           ` Yassine Oudjana
2022-08-29  9:31             ` AngeloGioacchino Del Regno

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