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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT009.mail.protection.outlook.com (10.13.175.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5293.13 via Frontend Transport; Wed, 25 May 2022 09:42:20 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Wed, 25 May 2022 04:42:05 -0500 From: Ravi Bangoria To: , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 02/13] perf/x86/amd: Add IBS OP_DATA2/3 register bit definitions Date: Wed, 25 May 2022 15:09:27 +0530 Message-ID: <20220525093938.4101-3-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220525093938.4101-1-ravi.bangoria@amd.com> References: <20220525093938.4101-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0ad10555-e877-4a5c-192f-08da3e32dd00 X-MS-TrafficTypeDiagnostic: BL1PR12MB5779:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2022 09:42:20.1529 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ad10555-e877-4a5c-192f-08da3e32dd00 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5779 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD IBS OP_DATA2 and OP_DATA3 provides detail about tagged load/store ops. Add definitions for these registers into header file. In addition to those, IBS_OP_DATA2 DataSrc provides detail about location of the data being accessed from by load ops. Define macros for legacy and extended DataSrc values. Signed-off-by: Ravi Bangoria --- arch/x86/include/asm/amd-ibs.h | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h index aabdbb5ab920..22184fe20cf0 100644 --- a/arch/x86/include/asm/amd-ibs.h +++ b/arch/x86/include/asm/amd-ibs.h @@ -6,6 +6,82 @@ #include +/* IBS_OP_DATA2 Bits */ +#define IBS_DATA_SRC_HI_SHIFT 6 +#define IBS_DATA_SRC_HI_MASK (0x3ULL << IBS_DATA_SRC_HI_SHIFT) +#define IBS_CACHE_HIT_ST_SHIFT 5 +#define IBS_CACHE_HIT_ST_MASK (0x1ULL << IBS_CACHE_HIT_ST_SHIFT) +#define IBS_RMT_NODE_SHIFT 4 +#define IBS_RMT_NODE_MASK (0x1ULL << IBS_RMT_NODE_SHIFT) +#define IBS_DATA_SRC_LO_SHIFT 0 +#define IBS_DATA_SRC_LO_MASK (0x7ULL << IBS_DATA_SRC_LO_SHIFT) + +/* IBS_OP_DATA2 DataSrc */ +#define IBS_DATA_SRC_LOC_CACHE 2 +#define IBS_DATA_SRC_DRAM 3 +#define IBS_DATA_SRC_REM_CACHE 4 +#define IBS_DATA_SRC_IO 7 + +/* IBS_OP_DATA2 with DataSrc Extension */ +#define IBS_DATA_SRC_EXT_LOC_CACHE 1 +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE 2 +#define IBS_DATA_SRC_EXT_DRAM 3 +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE 5 +#define IBS_DATA_SRC_EXT_PMEM 6 +#define IBS_DATA_SRC_EXT_IO 7 +#define IBS_DATA_SRC_EXT_EXT_MEM 8 +#define IBS_DATA_SRC_EXT_PEER_AGENT_MEM 12 + +/* IBS_OP_DATA3 Bits */ +#define IBS_TLB_REFILL_LAT_SHIFT 48 +#define IBS_TLB_REFILL_LAT_MASK (0xFFFFULL << IBS_TLB_REFILL_LAT_SHIFT) +#define IBS_DC_MISS_LAT_SHIFT 32 +#define IBS_DC_MISS_LAT_MASK (0xFFFFULL << IBS_DC_MISS_LAT_SHIFT) +#define IBS_OP_DC_MISS_OPEN_MEM_REQS_SHIFT 26 +#define IBS_OP_DC_MISS_OPEN_MEM_REQS_MASK (0x3FULL << IBS_OP_DC_MISS_OPEN_MEM_REQS_SHIFT) +#define IBS_OP_MEM_WIDTH_SHIFT 22 +#define IBS_OP_MEM_WIDTH_MASK (0xFULL << IBS_OP_MEM_WIDTH_SHIFT) +#define IBS_SW_PF_SHIFT 21 +#define IBS_SW_PF_MASK (0x1ULL << IBS_SW_PF_SHIFT) +#define IBS_L2_MISS_SHIFT 20 +#define IBS_L2_MISS_MASK (0x1ULL << IBS_L2_MISS_SHIFT) +#define IBS_DC_L2_TLB_HIT_1G_SHIFT 19 +#define IBS_DC_L2_TLB_HIT_1G_MASK (0x1ULL << IBS_DC_L2_TLB_HIT_1G_SHIFT) +#define IBS_DC_PHY_ADDR_VALID_SHIFT 18 +#define IBS_DC_PHY_ADDR_VALID_MASK (0x1ULL << IBS_DC_PHY_ADDR_VALID_SHIFT) +#define IBS_DC_LIN_ADDR_VALID_SHIFT 17 +#define IBS_DC_LIN_ADDR_VALID_MASK (0x1ULL << IBS_DC_LIN_ADDR_VALID_SHIFT) +#define IBS_DC_MISS_NO_MAB_ALLOC_SHIFT 16 +#define IBS_DC_MISS_NO_MAB_ALLOC_MASK (0x1ULL << IBS_DC_MISS_NO_MAB_ALLOC_SHIFT) +#define IBS_DC_LOCKED_OP_SHIFT 15 +#define IBS_DC_LOCKED_OP_MASK (0x1ULL << IBS_DC_LOCKED_OP_SHIFT) +#define IBS_DC_UC_MEM_ACC_SHIFT 14 +#define IBS_DC_UC_MEM_ACC_MASK (0x1ULL << IBS_DC_UC_MEM_ACC_SHIFT) +#define IBS_DC_WC_MEM_ACC_SHIFT 13 +#define IBS_DC_WC_MEM_ACC_MASK (0x1ULL << IBS_DC_WC_MEM_ACC_SHIFT) +#define IBS_DC_MIS_ACC_SHIFT 8 +#define IBS_DC_MIS_ACC_MASK (0x1ULL << IBS_DC_MIS_ACC_SHIFT) +#define IBS_DC_MISS_SHIFT 7 +#define IBS_DC_MISS_MASK (0x1ULL << IBS_DC_MISS_SHIFT) +#define IBS_DC_L2_TLB_HIT_2M_SHIFT 6 +#define IBS_DC_L2_TLB_HIT_2M_MASK (0x1ULL << IBS_DC_L2_TLB_HIT_2M_SHIFT) +/* + * Definition of 5-4 bits is different between Zen3 and Zen4 (Zen2 definition + * is same as Zen4) but the end result is same. So using Zen4 definition here. + */ +#define IBS_DC_L1_TLB_HIT_1G_SHIFT 5 +#define IBS_DC_L1_TLB_HIT_1G_MASK (0x1ULL << IBS_DC_L1_TLB_HIT_1G_SHIFT) +#define IBS_DC_L1_TLB_HIT_2M_SHIFT 4 +#define IBS_DC_L1_TLB_HIT_2M_MASK (0x1ULL << IBS_DC_L1_TLB_HIT_2M_SHIFT) +#define IBS_DC_L2_TLB_MISS_SHIFT 3 +#define IBS_DC_L2_TLB_MISS_MASK (0x1ULL << IBS_DC_L2_TLB_MISS_SHIFT) +#define IBS_DC_L1_TLB_MISS_SHIFT 2 +#define IBS_DC_L1_TLB_MISS_MASK (0x1ULL << IBS_DC_L1_TLB_MISS_SHIFT) +#define IBS_ST_OP_SHIFT 1 +#define IBS_ST_OP_MASK (0x1ULL << IBS_ST_OP_SHIFT) +#define IBS_LD_OP_SHIFT 0 +#define IBS_LD_OP_MASK (0x1ULL << IBS_LD_OP_SHIFT) + /* * IBS Hardware MSRs */ -- 2.31.1