From: "Paweł Anikiel" <pan@semihalf.com>
To: soc@kernel.org, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: arnd@arndb.de, olof@lixom.net, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, dinguyen@kernel.org,
"Paweł Anikiel" <pan@semihalf.com>,
"Alexandru M Stan" <amstan@chromium.org>
Subject: [PATCH 2/3] dts: socfpga: Add Google Chameleon v3 devicetree
Date: Mon, 30 May 2022 15:08:38 +0200 [thread overview]
Message-ID: <20220530130839.120710-3-pan@semihalf.com> (raw)
In-Reply-To: <20220530130839.120710-1-pan@semihalf.com>
Add devicetree for the Google Chameleon v3 board.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/socfpga_arria10_chameleonv3.dts | 90 +++++++++++++++++++
2 files changed, 91 insertions(+)
create mode 100644 arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 023c8b4ba45c..9417106d3289 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1146,6 +1146,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_chameleonv3.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644
index 000000000000..988cc445438e
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+ model = "Google Chameleon V3";
+ compatible = "google,chameleon-v3",
+ "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ ssm2603: ssm2603@1a {
+ compatible = "adi,ssm2603";
+ reg = <0x1a>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ u80: u80@21 {
+ compatible = "nxp,pca9535";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SOM_AUD_MUTE",
+ "DP1_OUT_CEC_EN",
+ "DP2_OUT_CEC_EN",
+ "DP1_SOM_PS8469_CAD",
+ "DPD_SOM_PS8469_CAD",
+ "DP_OUT_PWR_EN",
+ "STM32_RST_L",
+ "STM32_BOOT0",
+
+ "FPGA_PROT",
+ "STM32_FPGA_COMM0",
+ "TP119",
+ "TP120",
+ "TP121",
+ "TP122",
+ "TP123",
+ "TP124";
+ };
+};
+
+&mmc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
--
2.36.1.124.g0e6072fb45-goog
next prev parent reply other threads:[~2022-05-30 13:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-30 13:08 [PATCH 0/3] Add " Paweł Anikiel
2022-05-30 13:08 ` [PATCH 1/3] dts: socfpga: Change Mercury+ AA1 devicetree to header Paweł Anikiel
2022-05-30 18:55 ` Krzysztof Kozlowski
2022-05-31 12:43 ` Paweł Anikiel
2022-05-31 12:59 ` Krzysztof Kozlowski
2022-05-30 13:08 ` Paweł Anikiel [this message]
2022-05-30 18:56 ` [PATCH 2/3] dts: socfpga: Add Google Chameleon v3 devicetree Krzysztof Kozlowski
2022-05-31 1:20 ` Alexandru M Stan
2022-05-31 9:11 ` Krzysztof Kozlowski
2022-05-31 14:47 ` Paweł Anikiel
2022-05-31 15:36 ` Krzysztof Kozlowski
2022-06-01 7:40 ` Paweł Anikiel
2022-05-30 13:08 ` [PATCH 3/3] dt-bindings: altera: Update Arria 10 boards Paweł Anikiel
2022-05-30 18:58 ` Krzysztof Kozlowski
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