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[31.182.204.250]) by smtp.gmail.com with ESMTPSA id b8-20020ac247e8000000b004786321c697sm1056447lfp.138.2022.06.02.23.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 23:59:24 -0700 (PDT) From: =?UTF-8?q?Pawe=C5=82=20Anikiel?= To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, dinguyen@kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, amstan@chromium.org, upstream@semihalf.com, =?UTF-8?q?Pawe=C5=82=20Anikiel?= Subject: [PATCH v3 1/5] ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Date: Fri, 3 Jun 2022 08:58:12 +0200 Message-Id: <20220603065816.87952-2-pan@semihalf.com> X-Mailer: git-send-email 2.36.1.255.ge46751e96f-goog In-Reply-To: <20220603065816.87952-1-pan@semihalf.com> References: <20220603065816.87952-1-pan@semihalf.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Mercury+ AA1 is not a standalone board, rather it's a module with an Arria 10 SoC. Remove status = "okay" and i2c aliases, as they are routed to the base board and should be enabled from there. Signed-off-by: Paweł Anikiel --- arch/arm/boot/dts/Makefile | 1 - ...1.dts => socfpga_arria10_mercury_aa1.dtsi} | 28 ------------------- 2 files changed, 29 deletions(-) rename arch/arm/boot/dts/{socfpga_arria10_mercury_aa1.dts => socfpga_arria10_mercury_aa1.dtsi} (84%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index edfbedaa6168..023c8b4ba45c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1146,7 +1146,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ - socfpga_arria10_mercury_aa1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi similarity index 84% rename from arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts rename to arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index a75c059b6727..4b21351f2694 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -1,5 +1,4 @@ // SPDX-License-Identifier: GPL-2.0 -/dts-v1/; #include "socfpga_arria10.dtsi" @@ -11,8 +10,6 @@ / { aliases { ethernet0 = &gmac0; serial1 = &uart1; - i2c0 = &i2c0; - i2c1 = &i2c1; }; memory@0 { @@ -43,7 +40,6 @@ &gmac0 { phy-addr = <0xffffffff>; /* probe for phy addr */ max-frame-size = <3800>; - status = "okay"; phy-handle = <&phy3>; @@ -69,22 +65,8 @@ phy3: ethernet-phy@3 { }; }; -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - &i2c1 { - status = "okay"; isl12022: isl12022@6f { - status = "okay"; compatible = "isil,isl12022"; reg = <0x6f>; }; @@ -92,7 +74,6 @@ isl12022: isl12022@6f { /* Following mappings are taken from arria10 socdk dts */ &mmc { - status = "okay"; cap-sd-highspeed; broken-cd; bus-width = <4>; @@ -101,12 +82,3 @@ &mmc { &osc1 { clock-frequency = <33330000>; }; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; -- 2.36.1.255.ge46751e96f-goog