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[91.180.125.239]) by smtp.gmail.com with ESMTPSA id j3-20020a170906050300b006fed99e1143sm5242240eja.61.2022.06.05.09.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jun 2022 09:07:58 -0700 (PDT) From: Luc Van Oostenryck To: Arnd Bergmann Cc: Andrew Morton , linux-ia64@vger.kernel.org, linux-kernel@vger.kernel.org, "Paul E. McKenney" , Luc Van Oostenryck , kernel test robot , =?UTF-8?q?Toke=20H=C3=B8iland-J=C3=B8rgensen?= Subject: [PATCH] ia64: fix sparse warnings with cmpxchg() & xchg() Date: Sun, 5 Jun 2022 18:07:38 +0200 Message-Id: <20220605160738.79736-1-luc.vanoostenryck@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <87h7547k8c.fsf@toke.dk> References: <87h7547k8c.fsf@toke.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On IA64, new sparse's warnings where issued after fixing some __rcu annotations in kernel/bpf/. These new warnings are false positives and appear on IA64 because on this architecture, the macros for cmpxchg() and xchg() make casts that ignore sparse annotations. This patch contains the minimal patch to fix this issue: adding a missing cast and some missing '__force'. Link: https://lore.kernel.org/r/20220601120013.bq5a3ynbkc3hngm5@mail Reported-by: kernel test robot Cc: Toke Høiland-Jørgensen Signed-off-by: Luc Van Oostenryck --- Note: This patch is only compile tested on defconfig. The corresponding binary is unchanged (except some .rodata with the kernel version) as it should be. arch/ia64/include/uapi/asm/cmpxchg.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/ia64/include/uapi/asm/cmpxchg.h b/arch/ia64/include/uapi/asm/cmpxchg.h index 2c2f3cfeaa77..ca2e02685343 100644 --- a/arch/ia64/include/uapi/asm/cmpxchg.h +++ b/arch/ia64/include/uapi/asm/cmpxchg.h @@ -33,24 +33,24 @@ extern void ia64_xchg_called_with_bad_pointer(void); \ switch (size) { \ case 1: \ - __xchg_result = ia64_xchg1((__u8 *)ptr, x); \ + __xchg_result = ia64_xchg1((__u8 __force *)ptr, x); \ break; \ \ case 2: \ - __xchg_result = ia64_xchg2((__u16 *)ptr, x); \ + __xchg_result = ia64_xchg2((__u16 __force *)ptr, x); \ break; \ \ case 4: \ - __xchg_result = ia64_xchg4((__u32 *)ptr, x); \ + __xchg_result = ia64_xchg4((__u32 __force *)ptr, x); \ break; \ \ case 8: \ - __xchg_result = ia64_xchg8((__u64 *)ptr, x); \ + __xchg_result = ia64_xchg8((__u64 __force *)ptr, x); \ break; \ default: \ ia64_xchg_called_with_bad_pointer(); \ } \ - __xchg_result; \ + (__typeof__ (*(ptr)) __force) __xchg_result; \ }) #ifndef __KERNEL__ @@ -76,42 +76,42 @@ extern long ia64_cmpxchg_called_with_bad_pointer(void); \ switch (size) { \ case 1: \ - _o_ = (__u8) (long) (old); \ + _o_ = (__u8) (long __force) (old); \ break; \ case 2: \ - _o_ = (__u16) (long) (old); \ + _o_ = (__u16) (long __force) (old); \ break; \ case 4: \ - _o_ = (__u32) (long) (old); \ + _o_ = (__u32) (long __force) (old); \ break; \ case 8: \ - _o_ = (__u64) (long) (old); \ + _o_ = (__u64) (long __force) (old); \ break; \ default: \ break; \ } \ switch (size) { \ case 1: \ - _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_); \ + _r_ = ia64_cmpxchg1_##sem((__u8 __force *) ptr, new, _o_); \ break; \ \ case 2: \ - _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_); \ + _r_ = ia64_cmpxchg2_##sem((__u16 __force *) ptr, new, _o_); \ break; \ \ case 4: \ - _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_); \ + _r_ = ia64_cmpxchg4_##sem((__u32 __force *) ptr, new, _o_); \ break; \ \ case 8: \ - _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_); \ + _r_ = ia64_cmpxchg8_##sem((__u64 __force *) ptr, new, _o_); \ break; \ \ default: \ _r_ = ia64_cmpxchg_called_with_bad_pointer(); \ break; \ } \ - (__typeof__(old)) _r_; \ + (__typeof__(old) __force) _r_; \ }) #define cmpxchg_acq(ptr, o, n) \ -- 2.36.1