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Tue, 7 Jun 2022 01:57:08 -0700 Envelope-to: git@xilinx.com, wg@grandegger.com, mkl@pengutronix.de, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Received: from [10.140.6.18] (port=44264 helo=xhdlakshmis40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nyV1P-0007h1-So; Tue, 07 Jun 2022 01:57:08 -0700 From: Srinivas Neeli To: , , , , , , CC: , , , , , , , Srinivas Neeli Subject: [PATCH V2 2/2] can: xilinx_can: Add Transmitter delay compensation (TDC) feature support Date: Tue, 7 Jun 2022 14:26:54 +0530 Message-ID: <20220607085654.4178-3-srinivas.neeli@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220607085654.4178-1-srinivas.neeli@xilinx.com> References: <20220607085654.4178-1-srinivas.neeli@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 31660921-76f3-4e0d-058c-08da4863bc38 X-MS-TrafficTypeDiagnostic: BN8PR02MB5828:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2022 08:57:22.2315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31660921-76f3-4e0d-058c-08da4863bc38 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0014.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR02MB5828 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Added Transmitter delay compensation (TDC) feature support. In the case of higher measured loop delay with higher baud rates, observed bit stuff errors. By enabling the TDC feature in a controller, will compensate for the measure loop delay in the receive path. Signed-off-by: Srinivas Neeli --- drivers/net/can/xilinx_can.c | 46 +++++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index e179d311aa28..d0edd1bca33c 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* Xilinx CAN device driver * - * Copyright (C) 2012 - 2014 Xilinx, Inc. + * Copyright (C) 2012 - 2022 Xilinx, Inc. * Copyright (C) 2009 PetaLogix. All rights reserved. * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy * @@ -99,6 +99,7 @@ enum xcan_reg { #define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */ #define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */ #define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */ +#define XCAN_SR_TDCV_MASK 0x007F0000 /* TDCV Value */ #define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */ #define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */ #define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */ @@ -132,6 +133,8 @@ enum xcan_reg { #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */ /* CAN register bit shift - XCAN___SHIFT */ +#define XCAN_BRPR_TDCO_SHIFT 8 /* Transmitter Delay Compensation Offset */ +#define XCAN_BRPR_TDC_ENABLE BIT(16) /* Transmitter Delay Compensation (TDC) Enable */ #define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */ #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */ #define XCAN_BTR_SJW_SHIFT_CANFD 16 /* Synchronous jump width */ @@ -140,6 +143,7 @@ enum xcan_reg { #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */ #define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */ #define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */ +#define XCAN_SR_TDCV_SHIFT 16 /* TDCV Value */ /* CAN frame length constants */ #define XCAN_FRAME_MAX_DATA_LEN 8 @@ -276,6 +280,16 @@ static const struct can_bittiming_const xcan_data_bittiming_const_canfd2 = { .brp_inc = 1, }; +/* Transmission Delay Compensation constants for CANFD2.0 and Versal */ +static const struct can_tdc_const xcan_tdc_const = { + .tdcv_min = 0, + .tdcv_max = 0, /* Manual mode not supported. */ + .tdco_min = 0, + .tdco_max = 64, + .tdcf_min = 0, /* Filter window not supported */ + .tdcf_max = 0, +}; + /** * xcan_write_reg_le - Write a value to the device register little endian * @priv: Driver private data structure @@ -424,6 +438,11 @@ static int xcan_set_bittiming(struct net_device *ndev) priv->devtype.cantype == XAXI_CANFD_2_0) { /* Setting Baud Rate prescalar value in F_BRPR Register */ btr0 = dbt->brp - 1; + if (can_tdc_is_enabled(&priv->can)) { + btr0 = btr0 | + priv->can.tdc.tdco << XCAN_BRPR_TDCO_SHIFT | + XCAN_BRPR_TDC_ENABLE; + } /* Setting Time Segment 1 in BTR Register */ btr1 = dbt->prop_seg + dbt->phase_seg1 - 1; @@ -1483,6 +1502,23 @@ static int xcan_get_berr_counter(const struct net_device *ndev, return 0; } +/** + * xcan_get_auto_tdcv - Get Transmitter Delay Compensation Value + * @ndev: Pointer to net_device structure + * @tdcv: Pointer to TDCV value + * + * Return: 0 on success + */ +static int xcan_get_auto_tdcv(const struct net_device *ndev, u32 *tdcv) +{ + struct xcan_priv *priv = netdev_priv(ndev); + + *tdcv = (priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_TDCV_MASK) >> + XCAN_SR_TDCV_SHIFT; + + return 0; +} + static const struct net_device_ops xcan_netdev_ops = { .ndo_open = xcan_open, .ndo_stop = xcan_close, @@ -1734,18 +1770,22 @@ static int xcan_probe(struct platform_device *pdev) priv->can.do_get_berr_counter = xcan_get_berr_counter; priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_BERR_REPORTING; + priv->can.do_get_auto_tdcv = xcan_get_auto_tdcv; if (devtype->cantype == XAXI_CANFD) priv->can.data_bittiming_const = &xcan_data_bittiming_const_canfd; - if (devtype->cantype == XAXI_CANFD_2_0) + if (devtype->cantype == XAXI_CANFD_2_0) { priv->can.data_bittiming_const = &xcan_data_bittiming_const_canfd2; + priv->can.tdc_const = &xcan_tdc_const; + } if (devtype->cantype == XAXI_CANFD || devtype->cantype == XAXI_CANFD_2_0) - priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD; + priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | + CAN_CTRLMODE_TDC_AUTO; priv->reg_base = addr; priv->tx_max = tx_max; -- 2.25.1