From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BE7CC433EF for ; Wed, 8 Jun 2022 01:09:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1391076AbiFHBGW (ORCPT ); Tue, 7 Jun 2022 21:06:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382306AbiFGXjF (ORCPT ); Tue, 7 Jun 2022 19:39:05 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F66A1737D3 for ; Tue, 7 Jun 2022 14:36:30 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id 15-20020a63020f000000b003fca9ebc5cbso8958038pgc.22 for ; Tue, 07 Jun 2022 14:36:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=GmS2Zfk79J/Sy/RToehyTdCO4x0cZbdTb+j/zQ23WRQ=; b=bdzmq7UnnPvyPEMgI3dsae1dM+24A3NDnSWf4gIbLMniZ2r+Aq4+nRpXJeZPPB9xL8 PK2dP2sPhxm42na7Jm0Eep0e+8o5d5QH9UDPqbjcsE/VWDdOrTWQ2asiqtAsh3BmYVBz HFXIyvQgt7roQVy8YOrqw6ZqEAfovWah6OHIiWgSxODHxPCKVHdzC9QY9emiU80JH6c6 Pf9AY6vbYJZsdWVbS8Utv1IcJ6z3SCEdzpio9yHXPzxLYiTu0UudYuPUblOSgy2Kr46l fLzlCtqxY70zJB5zQcWyWFB+McvkwFLgrM4/v7DiqHrbVt1Y1Bqq3nqDXxLf26xzQ9Mh 90rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=GmS2Zfk79J/Sy/RToehyTdCO4x0cZbdTb+j/zQ23WRQ=; b=wKk5d0/nLHTRFEi6bM9TwPC4ufW96fEkYnZ9Und7+7mtNpYJrnv8PUsw7bP8+81ImH JQQeQ/RgVIhGS1BHtQ+cqW5M+ny2WSHyM9G+IMn+E1ycsasaizM/SekqZsae9FYm+aly uSB1jVxTuQpvSWfeewP3S+aXbZvDg49e/cOjHGSpj85FG8RfJ96Q0LP+bp9HVI4eMbZE Ur3FjMt1Qf5vnsUT/yEBKbsu2LcZUXn+FVsk2qHFih+6kUJIQfjrTbdIr3TPYyB+HlwL cz7PYJh05UprG7/n5KQNIoaA9F3rBBiL59B5zzaWtepPQUbeHT+N8MBaFCxIECIOvFL8 CqUQ== X-Gm-Message-State: AOAM531yotaXfwdlel39k1ovR7XhoXvfCBy0+vhH5zD2kXkoDpkiCOrj xAqPqJ8is8JVUnvC1unc4zs3SpqHMTo= X-Google-Smtp-Source: ABdhPJzLtIwGn7tXr8E4ox73+ncuEOoNaH720aApuV9kLjNuT2EKO4l6xAlZFYo1g5kpgraplK4mzENO8E8= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:903:2d0:b0:14d:8a8d:cb1 with SMTP id s16-20020a17090302d000b0014d8a8d0cb1mr30934054plk.50.1654637789914; Tue, 07 Jun 2022 14:36:29 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 7 Jun 2022 21:35:56 +0000 In-Reply-To: <20220607213604.3346000-1-seanjc@google.com> Message-Id: <20220607213604.3346000-8-seanjc@google.com> Mime-Version: 1.0 References: <20220607213604.3346000-1-seanjc@google.com> X-Mailer: git-send-email 2.36.1.255.ge46751e96f-goog Subject: [PATCH v5 07/15] KVM: VMX: Add helper to check if the guest PMU has PERF_GLOBAL_CTRL From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Eric Li , David Matlack , Oliver Upton Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a helper to check of the guest PMU has PERF_GLOBAL_CTRL, which is unintuitive _and_ diverges from Intel's architecturally defined behavior. Even worse, KVM currently implements the check using two different, but equivalent checksand , _and_ there has been at least one attempt to add a _third_ flavor. Link: https://lore.kernel.org/all/Yk4ugOETeo%2FqDRbW@google.com Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 4 ++-- arch/x86/kvm/vmx/vmx.h | 12 ++++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 5b85320fc9f1..6ce3b066f7d9 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -111,7 +111,7 @@ static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) { struct kvm_pmu *pmu = pmc_to_pmu(pmc); - if (pmu->version < 2) + if (!intel_pmu_has_perf_global_ctrl(pmu)) return true; return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); @@ -208,7 +208,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr, bool host_initiat case MSR_CORE_PERF_GLOBAL_OVF_CTRL: if (host_initiated) return true; - return pmu->version > 1; + return intel_pmu_has_perf_global_ctrl(pmu); break; case MSR_IA32_PEBS_ENABLE: if (host_initiated) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 576fed7e33de..215f17eb6732 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -91,6 +91,18 @@ union vmx_exit_reason { u32 full; }; +static inline bool intel_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu) +{ + /* + * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is + * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is + * greater than zero. However, KVM only exposes and emulates the MSR + * to/for the guest if the guest PMU supports at least "Architectural + * Performance Monitoring Version 2". + */ + return pmu->version > 1; +} + #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc) #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records) -- 2.36.1.255.ge46751e96f-goog