From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFF8ECCA48A for ; Wed, 8 Jun 2022 01:47:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1389764AbiFHBqQ (ORCPT ); Tue, 7 Jun 2022 21:46:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382466AbiFGXjF (ORCPT ); Tue, 7 Jun 2022 19:39:05 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 209DB1742B1 for ; Tue, 7 Jun 2022 14:36:32 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id i16-20020a170902cf1000b001540b6a09e3so10037554plg.0 for ; Tue, 07 Jun 2022 14:36:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=xglW57R7dPrxeD1+iu7KlOWod3vvDTBjvAqs2DB9Tyo=; b=Z8n2j8d/l+NC3N9+mbSwNLqH3Dk5xFYh3W8mbYfNzq6SnxKTw2miTYcRgW55MA898M tmofR+kdMmdNHI4Ukui4H9GO2TaNKM1ORixz8VRgMCvGIBmAFOimwOB+cmuXfel+5/Q8 wmI/GlXJFGuExnuB2R051rnXIKjHh8mXRiGXe0GsvU/ke6Z2UFuzAycPdzJLmrqYUVNt u0757aLcVkOOPfwGMK8VmL5NOw5E6tMyLH7XQY94dWQS5DUwDJMA4buwRvXpM0cNjGLX Ri77c5iIuMaAm6afVDTEFcuQgsRqJZPMXnoDhaUyRHigFNl1sYnLGmktT7uVpepWchos Hf9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=xglW57R7dPrxeD1+iu7KlOWod3vvDTBjvAqs2DB9Tyo=; b=lnbV0bKXOyIU7cIM48xlU0XdLOgzpQoUgj8i7rR3sGK3sWJ7n9GY3+qHwUSOFmwP5D ++iGOUZXnXxRyIHII7B3OFdh4Sh/dtlf9MHm5x9X0tqDBr/BhslJ7bzOWT4BG+Kb8zDY pB47cUcelhfm1jv39SQHWCoEYFmBQ5vbEAFsAsvztt1JbpYuR9x78IaMXtHAH+GczY9H 2n4OeddpWB7/Rz5WDCGD8sGReTLOL6EzzJKUm//w5ZZyNIE1/RaUUSr9g792Q47hd2T9 dAa5sLHww+KSaB2JNt+n0dfV1YvRblRGYc3i/Ig6JwnNlU7ojP+m+TX835ynncuOJR5N 6u6w== X-Gm-Message-State: AOAM533gv/TXH1txCkv4EkRRBLpT2kc9vmFTNxoAvhAQQVrCuDDnzsOk sKHxhSUr069G94aWg4PVAqOEtt5aiYc= X-Google-Smtp-Source: ABdhPJyYWskGfqg7Lzc1BANxoat/HX9oJuMU6eVjhdTVKgpGqjo/fAChIvEUAOBwu0ruJlwRyubKpPudm4k= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:902:9b8a:b0:163:d0ad:f9e8 with SMTP id y10-20020a1709029b8a00b00163d0adf9e8mr30305164plp.79.1654637791642; Tue, 07 Jun 2022 14:36:31 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 7 Jun 2022 21:35:57 +0000 In-Reply-To: <20220607213604.3346000-1-seanjc@google.com> Message-Id: <20220607213604.3346000-9-seanjc@google.com> Mime-Version: 1.0 References: <20220607213604.3346000-1-seanjc@google.com> X-Mailer: git-send-email 2.36.1.255.ge46751e96f-goog Subject: [PATCH v5 08/15] KVM: nVMX: Keep KVM updates to PERF_GLOBAL_CTRL ctrl bits across MSR write From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Eric Li , David Matlack , Oliver Upton Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Oliver Upton Since commit 03a8871add95 ("KVM: nVMX: Expose load IA32_PERF_GLOBAL_CTRL VM-{Entry,Exit} control"), KVM has taken ownership of the "load IA32_PERF_GLOBAL_CTRL" VMX entry/exit control bits. The ABI is that these bits will be set in the IA32_VMX_TRUE_{ENTRY,EXIT}_CTLS MSRs if the guest's CPUID exposes a vPMU that supports the IA32_PERF_GLOBAL_CTRL MSR (CPUID.0AH:EAX[7:0] > 1), and clear otherwise. However, commit aedbaf4f6afd ("KVM: x86: Extract kvm_update_cpuid_runtime() from kvm_update_cpuid()") partially broke KVM ownership of the aforementioned bits. Before, kvm_update_cpuid() was exercised frequently when running a guest and constantly applied its own changes to the "load IA32_PERF_GLOBAL_CTRL" bits. Now, the "load IA32_PERF_GLOBAL_CTRL" bits are only ever updated after a KVM_SET_CPUID/KVM_SET_CPUID2 ioctl, meaning that a subsequent MSR write from userspace will clobber these values. Note that older kernels without commit c44d9b34701d ("KVM: x86: Invoke vendor's vcpu_after_set_cpuid() after all common updates") still require that the entry/exit controls be updated from kvm_pmu_refresh(). Leave the benign call in place to allow for cleaner backporting and punt the cleanup to a later change. Uphold the old ABI by reapplying KVM's tweaks to the "load IA32_PERF_GLOBAL_CTRL" bits after an MSR write from userspace. Note, the old ABI that is being preserved is misguided KVM behavior that was introduced by commit 03a8871add95 ("KVM: nVMX: Expose load IA32_PERF_GLOBAL_CTRL VM-{Entry,Exit} control"). KVM's bogus tweaking of VMX MSRs was first implemented by commit 5f76f6f5ff96 ("KVM: nVMX: Do not expose MPX VMX controls when guest MPX disabled") to hack around a QEMU bug, and that bad behavior was unfortunately applied to PERF_GLOBAL_CTRL before it could be stamped out. Fixes: aedbaf4f6afd ("KVM: x86: Extract kvm_update_cpuid_runtime() from kvm_update_cpuid()") Reported-by: Jim Mattson Signed-off-by: Oliver Upton [sean: explicitly document the original KVM hack, set bits iff CPU supports the control] Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/vmx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 3f1671d7cbe4..73ec4746a4e6 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7413,6 +7413,20 @@ void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; } } + + /* + * KVM supports a 1-setting of the "load IA32_PERF_GLOBAL_CTRL" + * VM-{Entry,Exit} controls if the vPMU supports IA32_PERF_GLOBAL_CTRL. + */ + if (cpu_has_load_perf_global_ctrl()) { + if (intel_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu))) { + vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmx->nested.msrs.exit_ctls_high |= VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + } else { + vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; + vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; + } + } } static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) -- 2.36.1.255.ge46751e96f-goog