From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A640ECCA47E for ; Sat, 11 Jun 2022 00:59:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350679AbiFKA60 (ORCPT ); Fri, 10 Jun 2022 20:58:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344833AbiFKA6F (ORCPT ); Fri, 10 Jun 2022 20:58:05 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 482A469CD5 for ; Fri, 10 Jun 2022 17:58:04 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id s17-20020a170902ea1100b00168b7cad0efso366812plg.14 for ; Fri, 10 Jun 2022 17:58:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=AVQRubkzoQn/ed1EYoJH5pfC/v1u5yrl7rOVcK+kmGE=; b=VRiSwc2//odTKj+Eikd4OHXG3B/142UyF51ul2JgNOdEGUo27qch42urrIwYQjX4X0 W3gjMlZ1sC/ZFB3Bpv2KccjO+6a+Ac+T6bLDwX8aH3pdYjMTC3sSZlxtYuEr/xamNZDe 00w417jax+aMFmj9dabWcc49lg4BxoAYUQUp/Ub4Ut5gsAC/NlQSiHazeVfgNhoSEB/a QemA8PXGPECUB1ZtbxB2aHZzNcGTy+qOID+luCycolJUSGx+NH6P7BFmCufYtVF7W6zN +y6YQ6iySYfkV6AhhkZwNQ4SGYrH0kWRjb3JrFfKNZW/8sZoxxv0aXHbKqoYft+qR/dq q3GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=AVQRubkzoQn/ed1EYoJH5pfC/v1u5yrl7rOVcK+kmGE=; b=7NKCmtJw7VdSj8ihXA9h7VmE6b/dFj63bLrx5YfNL1v63WrxihWjpNqNLm8OTAOTkU ysHVM1NyE5KO6tgLe+lEQpKSQpvndspAAKZqnKDbXIQQHuXJOeHTThayV7ECQwfqc9JX Ygdeh2NOUC9sOyPlXCUTsh8Bb3mqpTpIbgYNcr5sPHtc2OirhM5mkd63eRWmiUdZ/5Dt UUg5xX23dMB5Y+a5KVmL1bgCyn+M7Q5ZoU3N9pRvF3y/XYesGwgwLqkIgipXGcdV5+Qe Jzwi3Ln8HoCeuaEI2dF+y9AuT+f9Q4MTpvpTsOgPo2osPx6zZpQ6hnbjqMyZCdPfqihV ukdQ== X-Gm-Message-State: AOAM532NBoweZBv4CA8Dg8AJW7A83qD0c+IrmHQcHkBXOZtLuc9u37nv hczA8RdHEZ0j7WHoJS0i9Mws2CxHBEU= X-Google-Smtp-Source: ABdhPJz0VXKGAmbpeP1mI8hPMgAEsThaF7yFOUoQL4dG2YifgaHvI+1U0YLnaVaH7A8lar4qT043gNdIaI0= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:90a:178f:b0:1e3:3ba:c185 with SMTP id q15-20020a17090a178f00b001e303bac185mr13438pja.1.1654909083306; Fri, 10 Jun 2022 17:58:03 -0700 (PDT) Reply-To: Sean Christopherson Date: Sat, 11 Jun 2022 00:57:51 +0000 In-Reply-To: <20220611005755.753273-1-seanjc@google.com> Message-Id: <20220611005755.753273-4-seanjc@google.com> Mime-Version: 1.0 References: <20220611005755.753273-1-seanjc@google.com> X-Mailer: git-send-email 2.36.1.476.g0c4daa206d-goog Subject: [PATCH 3/7] Revert "KVM: x86/pmu: Accept 0 for absent PMU MSRs when host-initiated if !enable_pmu" From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Eating reads and writes to all "PMU" MSRs when there is no PMU is wildly broken as it results in allowing accesses to _any_ MSR on Intel CPUs as intel_is_valid_msr() returns true for all host_initiated accesses. A revert of commit d1c88a402056 ("KVM: x86: always allow host-initiated writes to PMU MSRs") will soon follow. This reverts commit 8e6a58e28b34e8d247e772159b8fa8f6bae39192. Signed-off-by: Sean Christopherson --- arch/x86/kvm/pmu.c | 8 -------- arch/x86/kvm/svm/pmu.c | 11 +---------- 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 6a32092460d3..87483e503c46 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -442,19 +442,11 @@ static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr) int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { - if (msr_info->host_initiated && !vcpu->kvm->arch.enable_pmu) { - msr_info->data = 0; - return 0; - } - return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info); } int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { - if (msr_info->host_initiated && !vcpu->kvm->arch.enable_pmu) - return !!msr_info->data; - kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info); } diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index fe520b2649b5..256244b8f89c 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -182,16 +182,7 @@ static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr, bool host_initiated) { /* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough. */ - if (!host_initiated) - return false; - - switch (msr) { - case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: - case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: - return true; - default: - return false; - } + return false; } static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) -- 2.36.1.476.g0c4daa206d-goog