From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24AAECCA47A for ; Tue, 14 Jun 2022 23:33:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241260AbiFNXdl (ORCPT ); Tue, 14 Jun 2022 19:33:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237951AbiFNXdh (ORCPT ); Tue, 14 Jun 2022 19:33:37 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 197F44CD65 for ; Tue, 14 Jun 2022 16:33:35 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id n8-20020a170902d2c800b001663868e2c2so5545584plc.21 for ; Tue, 14 Jun 2022 16:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:message-id:mime-version:subject:from:to:cc; bh=RLjwpUgrQld2IadGR7ke2jwP+ko9Ytby9Ifc1yeHho4=; b=NnrFOmxaXlolnOZ4zOwyM45sGetWmK8pBfOzGCq4bgATHK4Q6cUg4JW1FEPkRPokQi EdPGSF2vSW/TgXhoawsV4hlkoIHznqpUb+ejtk3jWlp47BQAq4Dve5HRLrYj5W+763Ri W+W2CLhOS/fsml+8SiyNl6Rln2HVRUPFIonQ6mQSalHkU7jkadF5Bz9k8znncsk5JkWv WUpTOe+p0J+LNiVDqdZR20bN09ExUOzOdtTYOSuFerW/1Dr0xZiO2A+r6O+GSRfR0AcY zRZA7+hgFHsqhTXWg3ETn4h0MGi5bYycsK2buTdLZBCVzNLKPRMF2DuBZctunw8h1GZR J62Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:message-id:mime-version:subject :from:to:cc; bh=RLjwpUgrQld2IadGR7ke2jwP+ko9Ytby9Ifc1yeHho4=; b=3Q683MeqtHt5+a7LsXxcgrU68VBdS0iKYgtfmtvmYkHenLIgds8wnvQizxoKUHmxzn UquHJYs6IqBgJ13YhyQLbKw4C0NldWpQl3QTpq6JMgnAfUaKJ5SgfTCGDmCjV2FgZynQ jVQwbR5rAALf80kOS8lGxnfSvqBm1i+PY+Eh7pmcTcLFMTLPZOKRyjlIej+AF2fecGfY BBUZU4jttaU2PTbWGwQWRB3K94P+2cQN5WySespAbeXzLK5Sjuzc6WN31Prg1/5pIv+z UlmORoqb1efqbqFCYQCuuEPE2Xr/138UN4LKCns1PSb/bnQHnlEt63978flTK/shmBZj kH8g== X-Gm-Message-State: AOAM532j9nD9maoauwaZ+Zyi3x8LZnotDkjCt4ZYBt9wreUZfiUp4jDJ k6bqvU8Xu85VxP95sIuAvsJR6Co0NpA= X-Google-Smtp-Source: ABdhPJwjXKQDy2nT+/ZoD3beslO/H0/x3QOlGWxUvBo5PFi+sUG33Ct3ksHIiH+NdOOnGIgytN5xJK6kki8= X-Received: from seanjc.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:3e5]) (user=seanjc job=sendgmr) by 2002:a17:902:c951:b0:166:4f65:cff2 with SMTP id i17-20020a170902c95100b001664f65cff2mr6552735pla.7.1655249614340; Tue, 14 Jun 2022 16:33:34 -0700 (PDT) Reply-To: Sean Christopherson Date: Tue, 14 Jun 2022 23:33:20 +0000 Message-Id: <20220614233328.3896033-1-seanjc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.36.1.476.g0c4daa206d-goog Subject: [PATCH v2 0/8] KVM: x86/mmu: Use separate namespaces gPTEs and SPTEs From: Sean Christopherson To: Paolo Bonzini Cc: Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Lai Jiangshan Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is based on kvm/queue + "Remove unused PT32_DIR_BASE_ADDR_MASK from mmu.c", so I think it should apply cleanly on top of what you already grabbed. Clean up the x86 MMU code to use separate namespaces for guest PTEs and shadow PTEs. While there is most definitely overlap, especially in attribute bits, the rules for walking gPTEs and for generating/walking SPTEs differ in subtle ways, e.g. see commit fc9bf2e087ef ("KVM: x86/mmu: Do not apply HPA (memory encryption) mask to GPAs"). The paging32 macros in particular should never be used outside of paging_tmpl.h. Separating gPTEs from SPTEs actually provides for nice cleanups (see the diffstat) as KVM has ended up with a fair bit of copy+paste code that can be deduplicated once KVM isn't trying to use PT64_* defines for both gPTEs and SPTEs. This is a spiritual successor to patches 4-7 of the series[*] that added the aformentenioned commit. v2: - Don't move is_cpuid_PSE36(). [Lai Jiangshan] - Change author for patch 1 (yeah, I was lazy). [Lai Jiangshan] - Fix a random typo in patch 7's changelog. - Rebase to play nice with PT32_DIR_BASE_ADDR_MASK. v1: https://lore.kernel.org/all/20220613225723.2734132-2-seanjc@google.com [*] https://lore.kernel.org/all/20210623230552.4027702-1-seanjc@google.com Lai Jiangshan (1): KVM: x86/mmu: Drop unused CMPXCHG macro from paging_tmpl.h Sean Christopherson (7): KVM: VMX: Refactor 32-bit PSE PT creation to avoid using MMU macro KVM: x86/mmu: Bury 32-bit PSE paging helpers in paging_tmpl.h KVM: x86/mmu: Dedup macros for computing various page table masks KVM: x86/mmu: Use separate namespaces for guest PTEs and shadow PTEs KVM: x86/mmu: Use common macros to compute 32/64-bit paging masks KVM: x86/mmu: Truncate paging32's PT_BASE_ADDR_MASK to 32 bits KVM: x86/mmu: Use common logic for computing the 32/64-bit base PA mask arch/x86/kvm/mmu.h | 10 ------ arch/x86/kvm/mmu/mmu.c | 57 +++++++++------------------------ arch/x86/kvm/mmu/mmu_internal.h | 17 ++++++++++ arch/x86/kvm/mmu/paging.h | 14 -------- arch/x86/kvm/mmu/paging_tmpl.h | 55 ++++++++++++++++--------------- arch/x86/kvm/mmu/spte.c | 2 +- arch/x86/kvm/mmu/spte.h | 28 +++++++--------- arch/x86/kvm/mmu/tdp_iter.c | 6 ++-- arch/x86/kvm/mmu/tdp_mmu.c | 6 ++-- arch/x86/kvm/vmx/vmx.c | 2 +- 10 files changed, 82 insertions(+), 115 deletions(-) delete mode 100644 arch/x86/kvm/mmu/paging.h base-commit: ccf1c220033d8d6fe50d8d11daa3dec5640f8c4d -- 2.36.1.476.g0c4daa206d-goog