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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id m14-20020adfdc4e000000b0021a3c960214sm9189510wrj.6.2022.06.19.09.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jun 2022 09:50:21 -0700 (PDT) From: Conor Dooley To: Michael Turquette , Stephen Boyd , Conor Dooley , Philipp Zabel , Geert Uytterhoeven Cc: Daire McNamara , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC 4/6] reset: add polarfire soc reset support Date: Sun, 19 Jun 2022 17:49:34 +0100 Message-Id: <20220619164935.1492823-5-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220619164935.1492823-1-mail@conchuod.ie> References: <20220619164935.1492823-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Conor Dooley Add support for the resets on Microchip's PolarFire SoC (MPFS). Reset control is a single register, wedged in between registers for clock control. To fit with existed DT etc, the reset controller is created using the aux device framework & set up in the clock driver. Signed-off-by: Conor Dooley --- drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 155 +++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 drivers/reset/reset-mpfs.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 93c8d07ee328..8f7d7cda690d 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -122,6 +122,15 @@ config RESET_MCHP_SPARX5 help This driver supports switch core reset for the Microchip Sparx5 SoC. +config RESET_POLARFIRE_SOC + bool "Microchip PolarFire SoC (MPFS) Reset Driver" + depends on AUXILIARY_BUS + default MCHP_CLK_MPFS + help + This driver supports switch core reset for the Microchip PolarFire SoC + + CONFIG_RESET_MPFS + config RESET_MESON tristate "Meson Reset Driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index a80a9c4008a7..5fac3a753858 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_RESET_K210) += reset-k210.o obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o +obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) += reset-npcm.o @@ -38,4 +39,3 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o - diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c new file mode 100644 index 000000000000..6c9c10cd9077 --- /dev/null +++ b/drivers/reset/reset-mpfs.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PolarFire SoC (MPFS) Peripheral Clock Reset Controller + * + * Author: Conor Dooley + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * The ENVM reset is the lowest bit in the register & I am using the CLK_FOO + * defines in the dt to make things easier to configure - so this is accounting + * for the offset of 3 there. + */ +#define MPFS_PERIPH_OFFSET CLK_ENVM +#define MPFS_NUM_RESETS 30u + +/* + * Peripheral clock resets + */ + +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + u32 reg; + + reg = mpfs_reset_read(rcdev->dev); + reg |= (1u << id); + mpfs_reset_write(rcdev->dev, reg); + + dev_dbg(rcdev->dev, + "Asserting reset for device with REG_SUBBLK_RESET_CR index: %u\n", + id); + return 0; +} + +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + u32 reg, val; + + reg = mpfs_reset_read(rcdev->dev); + val = reg & ~(1u << id); + mpfs_reset_write(rcdev->dev, val); + + dev_dbg(rcdev->dev, + "Deasserting device with REG_SUBBLK_RESET_CR index: %u\n", + id); + + return 0; +} + +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + u32 reg = mpfs_reset_read(rcdev->dev); + + return (reg & (1u << id)); +} + +static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + dev_dbg(rcdev->dev, + "Resetting device with REG_SUBBLK_RESET_CR index: %u\n", + id); + + mpfs_assert(rcdev, id); + + /* Value is stolen from the rcar reset driver, will need changing after RFC */ + udelay(35); + + mpfs_deassert(rcdev, id); + + return 0; +} + +static const struct reset_control_ops mpfs_reset_ops = { + .reset = mpfs_reset, + .assert = mpfs_assert, + .deassert = mpfs_deassert, + .status = mpfs_status, +}; + +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + unsigned int index = reset_spec->args[0]; + + /* + * CLK_RESERVED does not map to a clock, but it does map to a reset, + * so it has to be accounted for here. It is the reset for the fabric, + * so if this reset gets called - do not reset it. + */ + if (index == CLK_RESERVED) { + dev_err(rcdev->dev, "Resetting the fabric is not supported\n"); + return -EINVAL; + } + + if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) { + dev_err(rcdev->dev, "Invalid reset index %u\n", reset_spec->args[0]); + return -EINVAL; + } + + return index - MPFS_PERIPH_OFFSET; +} + +static int mpfs_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev = &adev->dev; + struct reset_controller_dev *rcdev; + int ret; + + rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + return -ENOMEM; + + rcdev->dev = dev; + rcdev->dev->parent = adev->dev.parent; + rcdev->ops = &mpfs_reset_ops; + rcdev->of_node = adev->dev.parent->of_node; + rcdev->of_reset_n_cells = 1; + rcdev->of_xlate = mpfs_reset_xlate; + rcdev->nr_resets = MPFS_NUM_RESETS; + + ret = devm_reset_controller_register(dev, rcdev); + if (!ret) + dev_info(dev, "Registered MPFS reset controller\n"); + + return ret; +} + +static const struct auxiliary_device_id mpfs_reset_ids[] = { + { + .name = "clk_mpfs.reset-mpfs", + }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids); + +static struct auxiliary_driver mpfs_reset_driver = { + .probe = mpfs_reset_probe, + .id_table = mpfs_reset_ids, +}; + +module_auxiliary_driver(mpfs_reset_driver); + +MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(MCHP_CLK_MPFS); -- 2.36.1