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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id m14-20020adfdc4e000000b0021a3c960214sm9189510wrj.6.2022.06.19.09.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jun 2022 09:50:22 -0700 (PDT) From: Conor Dooley To: Michael Turquette , Stephen Boyd , Conor Dooley , Philipp Zabel , Geert Uytterhoeven Cc: Daire McNamara , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC 5/6] net: macb: add polarfire soc reset support Date: Sun, 19 Jun 2022 17:49:35 +0100 Message-Id: <20220619164935.1492823-6-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220619164935.1492823-1-mail@conchuod.ie> References: <20220619164935.1492823-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Conor Dooley To date, the Microchip PolarFire SoC (MPFS) has been using the cdns,macb compatible, however the generic device does not have reset support. Add a new compatible & .data for MPFS to hook into the reset functionality added for zynqmp support (and make the zynqmp init function generic in the process). Signed-off-by: Conor Dooley --- drivers/net/ethernet/cadence/macb_main.c | 25 +++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index d89098f4ede8..325f0463fd42 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4689,33 +4689,32 @@ static const struct macb_config np4_config = { .usrio = &macb_default_usrio, }; -static int zynqmp_init(struct platform_device *pdev) +static int init_reset_optional(struct platform_device *pdev) { struct net_device *dev = platform_get_drvdata(pdev); struct macb *bp = netdev_priv(dev); int ret; if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { - /* Ensure PS-GTR PHY device used in SGMII mode is ready */ + /* Ensure PHY device used in SGMII mode is ready */ bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL); if (IS_ERR(bp->sgmii_phy)) { ret = PTR_ERR(bp->sgmii_phy); dev_err_probe(&pdev->dev, ret, - "failed to get PS-GTR PHY\n"); + "failed to get SGMII PHY\n"); return ret; } ret = phy_init(bp->sgmii_phy); if (ret) { - dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n", + dev_err(&pdev->dev, "failed to init SGMII PHY: %d\n", ret); return ret; } } - /* Fully reset GEM controller at hardware level using zynqmp-reset driver, - * if mapped in device tree. + /* Fully reset controller at hardware level if mapped in device tree */ ret = device_reset_optional(&pdev->dev); if (ret) { @@ -4737,7 +4736,7 @@ static const struct macb_config zynqmp_config = { MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH, .dma_burst_length = 16, .clk_init = macb_clk_init, - .init = zynqmp_init, + .init = init_reset_optional, .jumbo_max_len = 10240, .usrio = &macb_default_usrio, }; @@ -4751,6 +4750,17 @@ static const struct macb_config zynq_config = { .usrio = &macb_default_usrio, }; +static const struct macb_config mpfs_config = { + .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | + MACB_CAPS_JUMBO | + MACB_CAPS_GEM_HAS_PTP, + .dma_burst_length = 16, + .clk_init = macb_clk_init, + .init = init_reset_optional, + .usrio = &macb_default_usrio, + .jumbo_max_len = 10240, +}; + static const struct macb_config sama7g5_gem_config = { .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG | MACB_CAPS_MIIONRGMII, @@ -4787,6 +4797,7 @@ static const struct of_device_id macb_dt_ids[] = { { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, { .compatible = "cdns,zynq-gem", .data = &zynq_config }, { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, + { .compatible = "microchip,mpfs-macb", .data = &mpfs_config }, { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, { /* sentinel */ } -- 2.36.1