From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6EACC433EF for ; Tue, 21 Jun 2022 07:41:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347797AbiFUHk4 (ORCPT ); Tue, 21 Jun 2022 03:40:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347837AbiFUHki (ORCPT ); Tue, 21 Jun 2022 03:40:38 -0400 Received: from forward500o.mail.yandex.net (forward500o.mail.yandex.net [IPv6:2a02:6b8:0:1a2d::610]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D777F23BDC for ; Tue, 21 Jun 2022 00:40:35 -0700 (PDT) Received: from myt6-93965afc2133.qloud-c.yandex.net (myt6-93965afc2133.qloud-c.yandex.net [IPv6:2a02:6b8:c12:5525:0:640:9396:5afc]) by forward500o.mail.yandex.net (Yandex) with ESMTP id CD00D940DAC; Tue, 21 Jun 2022 10:40:33 +0300 (MSK) Received: from myt5-01d0fbe499ab.qloud-c.yandex.net (myt5-01d0fbe499ab.qloud-c.yandex.net [2a02:6b8:c12:4619:0:640:1d0:fbe4]) by myt6-93965afc2133.qloud-c.yandex.net (mxback/Yandex) with ESMTP id DqjiMbBwxe-eWh05tEC; Tue, 21 Jun 2022 10:40:33 +0300 X-Yandex-Fwd: 2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1655797233; bh=RdX/+yTKrxFGxvASlWbAzAdqYEzzocthfBSsMMgNr3Y=; h=In-Reply-To:Subject:Cc:To:From:References:Date:Message-ID; b=Qy4sYZrHWLy5aniM2Q8DLanUFI2lgGMlIcLBMZOvtbwlm7YyrxUEHTcfljkQpY0id q89bdZ8psW9qhCz159ety4bcuXPib6E965hdu9hgKWU5MWpeAOg6n/PQa0bz2W7e4A KgXh1+wx9D3ICmQgv+YD//brfOeeNQ0JECFWaJ44= Authentication-Results: myt6-93965afc2133.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by myt5-01d0fbe499ab.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id zSjiCSJHOL-eVMWsID8; Tue, 21 Jun 2022 10:40:32 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) Date: Tue, 21 Jun 2022 10:40:30 +0300 From: Nikita Shubin To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Arnd Bergmann , Atish Patra , Heinrich Schuchardt , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output Message-ID: <20220621104030.349c570b@redslave.neermore.group> In-Reply-To: <20220620115549.1529597-1-apatel@ventanamicro.com> References: <20220620115549.1529597-1-apatel@ventanamicro.com> X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Anup! On Mon, 20 Jun 2022 17:25:49 +0530 Anup Patel wrote: > Identifying the underlying RISC-V implementation can be important > for some of the user space applications. For example, the perf tool > uses arch specific CPU implementation id (i.e. CPUID) to select a > JSON file describing custom perf events on a CPU. > > Currently, there is no way to identify RISC-V implementation so we > add mvendorid, marchid, and mimpid to /proc/cpuinfo output. Tested on Sifive Unmatched: localhost / # cat /proc/cpuinfo processor : 0 hart : 4 isa : rv64imafdc mmu : sv39 uarch : sifive,bullet0 mvendorid : 0x489 marchid : 0x8000000000000007 mimpid : 0x20181004 processor : 1 hart : 1 isa : rv64imafdc mmu : sv39 uarch : sifive,bullet0 mvendorid : 0x489 marchid : 0x8000000000000007 mimpid : 0x20181004 processor : 2 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,bullet0 mvendorid : 0x489 marchid : 0x8000000000000007 mimpid : 0x20181004 processor : 3 hart : 3 isa : rv64imafdc mmu : sv39 uarch : sifive,bullet0 mvendorid : 0x489 marchid : 0x8000000000000007 mimpid : 0x20181004 mvendorid, marchid values match the register description in u74 manual. mimpid seems to be ok, through i can't find exact in U74/Unmatched docs. Tested-by: Nikita Shubin > > Signed-off-by: Anup Patel > --- > arch/riscv/kernel/cpu.c | 51 > +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 > insertions(+) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index fba9e9f46a8c..c037b8691bbb 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -3,10 +3,13 @@ > * Copyright (C) 2012 Regents of the University of California > */ > > +#include > #include > #include > #include > +#include > #include > +#include > #include > #include > > @@ -64,6 +67,50 @@ int riscv_of_parent_hartid(struct device_node > *node) } > > #ifdef CONFIG_PROC_FS > + > +struct riscv_cpuinfo { > + unsigned long mvendorid; > + unsigned long marchid; > + unsigned long mimpid; > +}; > +static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > + > +static int riscv_cpuinfo_starting(unsigned int cpu) > +{ > + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > + > +#if defined(CONFIG_RISCV_SBI) > + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > + ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); > +#elif defined(CONFIG_RISCV_M_MODE) > + ci->mvendorid = csr_read(CSR_MVENDORID); > + ci->marchid = csr_read(CSR_MARCHID); > + ci->mimpid = csr_read(CSR_MIMPID); > +#else > + ci->mvendorid = 0; > + ci->marchid = 0; > + ci->mimpid = 0; > +#endif > + > + return 0; > +} > + > +static int __init riscv_cpuinfo_init(void) > +{ > + int ret; > + > + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, > "riscv/cpuinfo:starting", > + riscv_cpuinfo_starting, NULL); > + if (ret < 0) { > + pr_err("cpuinfo: failed to register hotplug > callbacks.\n"); > + return ret; > + } > + > + return 0; > +} > +device_initcall(riscv_cpuinfo_init); > + > #define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ > { \ > .uprop = #UPROP, \ > @@ -178,6 +225,7 @@ static int c_show(struct seq_file *m, void *v) > { > unsigned long cpu_id = (unsigned long)v - 1; > struct device_node *node = of_get_cpu_node(cpu_id, NULL); > + struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, > cpu_id); const char *compat, *isa; > > seq_printf(m, "processor\t: %lu\n", cpu_id); > @@ -188,6 +236,9 @@ static int c_show(struct seq_file *m, void *v) > if (!of_property_read_string(node, "compatible", &compat) > && strcmp(compat, "riscv")) > seq_printf(m, "uarch\t\t: %s\n", compat); > + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); > + seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); > + seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); > seq_puts(m, "\n"); > of_node_put(node); >