From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A40E7C43334 for ; Wed, 22 Jun 2022 16:22:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376584AbiFVQWz (ORCPT ); Wed, 22 Jun 2022 12:22:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358571AbiFVQWp (ORCPT ); Wed, 22 Jun 2022 12:22:45 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFFAA3F32F for ; Wed, 22 Jun 2022 09:22:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655914964; x=1687450964; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eoYteC6GODz7y0R2zobgy/O4IaLSlJbZw9u65ssKePw=; b=DqXRHleFkKczJTc04BB5mP7fKVh0jGU2GpnHAimmuHRxLmBsjN2I87Mz qkcPFeWBQtCAqWL+VLPZ5YjeJX1KJ7myrUWo/puij9+47jRYgz2nbzASb m4odh0DIxzgNjrl39AKrr0ROC+WT/RQPezw75/QQUAO9ou3P6bVbkknpZ FRFOwN3h0B34DLWngV8YFK4TlZQffA7tA1XuFgkFUvbLfTj7EW9hq6Wr0 8UW3uDFrbuw5E5uy/BuZsZNfnEaeiiSKVovkPgceobta4EEdTr/d8Uk+B Bc1t9+MYaaU7IbBM6vj/4ksGdqex09jmGpqQaO7wyvMgK16t4eiHvBfMU g==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="344457065" X-IronPort-AV: E=Sophos;i="5.92,212,1650956400"; d="scan'208";a="344457065" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2022 09:22:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,212,1650956400"; d="scan'208";a="677632041" Received: from black.fi.intel.com ([10.237.72.28]) by FMSMGA003.fm.intel.com with ESMTP; 22 Jun 2022 09:22:38 -0700 Received: by black.fi.intel.com (Postfix, from userid 1000) id 28B0E67; Wed, 22 Jun 2022 19:22:43 +0300 (EEST) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv4 1/8] x86/mm: Fix CR3_ADDR_MASK Date: Wed, 22 Jun 2022 19:22:23 +0300 Message-Id: <20220622162230.83474-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220622162230.83474-1-kirill.shutemov@linux.intel.com> References: <20220622162230.83474-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The mask must not include bits above physical address mask. These bits are reserved and can be used for other things. Bits 61 and 62 are used for Linear Address Masking. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe --- arch/x86/include/asm/processor-flags.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index 02c2cbda4a74..a7f3d9100adb 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -35,7 +35,7 @@ */ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63) -- 2.35.1