Re: [PATCH v2] fpga: altera-cvp: Truncated bitstream error support

[tien.sung.ang@intel.com]

> > Though without doubt, your solution is doable, I have a 
> > discussion with the Intel architect and they insisted that
> > the device driver must not make such a decision. The decision to 
> > drop or accept a transfer is up to the firmware. The firmware

> Why dropping or accepting is forbidden, but padding is allowed? If the
> decision is no operation to the data, then padding should also be
> forbidden.

> > insisted that the buffer be padded with whatever value. They

> If I understand right, the 2 decisions are conflicted. On one hand,
> the driver should not care about the data. On another hand, the
> driver should still care about the data for some rule.

> So please firstly reach your agreement before making patches.

Had some delays in replying,from the perspective of the driver, 
Intel architects want it to be just purely on the transfer of 
data without inspecting the data. 
If the size of a transfer is 4096bytes, we can padd it. 
I can do that which I think it is not an issue.
Let me create a reworked patch to pad the payload with Zeros.
Would this be OK for patch v3?

> > Yes, it could look confusing to other programmers. And, yes, the 
> > padding doesn't matter. Let me relook into this. As the driver is 
> > already re-tested by the silicon validatioin. 
> > I want to avoid making any change as it
> > would meant another couple of weeks of re-testing. 
> > Can this be accepted as it is?

> Sorry, I can't. Some clarification is needed.

Reply as above, let us implement the padding in the
next patch v3. Appreciate your inputs. Thanks