From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2936C433EF for ; Wed, 29 Jun 2022 18:48:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230480AbiF2Ssh (ORCPT ); Wed, 29 Jun 2022 14:48:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229948AbiF2SsZ (ORCPT ); Wed, 29 Jun 2022 14:48:25 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1B7D4272 for ; Wed, 29 Jun 2022 11:48:23 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1D9B41480; Wed, 29 Jun 2022 11:48:23 -0700 (PDT) Received: from bogus (unknown [10.57.39.193]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B330A3F5A1; Wed, 29 Jun 2022 11:48:19 -0700 (PDT) Date: Wed, 29 Jun 2022 19:47:08 +0100 From: Sudeep Holla To: Conor.Dooley@microchip.com Cc: linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, atishp@atishpatra.org, atishp@rivosinc.com, vincent.guittot@linaro.org, dietmar.eggemann@arm.com, wangqing@vivo.com, robh+dt@kernel.org, rafael@kernel.org, ionela.voinescu@arm.com, pierre.gondois@arm.com, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, gshan@redhat.com, Valentina.FernandezAlanis@microchip.com Subject: Re: [PATCH v5 09/19] arch_topology: Use the last level cache information from the cacheinfo Message-ID: <20220629184708.x5exgjoy4sblyqml@bogus> References: <20220627165047.336669-1-sudeep.holla@arm.com> <20220627165047.336669-10-sudeep.holla@arm.com> <3656a067-cc3f-fd5b-e339-5925a856cce1@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3656a067-cc3f-fd5b-e339-5925a856cce1@microchip.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 29, 2022 at 06:18:25PM +0000, Conor.Dooley@microchip.com wrote: > On 29/06/2022 18:49, Conor.Dooley@microchip.com wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > On 27/06/2022 17:50, Sudeep Holla wrote: > >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > >> > >> The cacheinfo is now initialised early along with the CPU topology > >> initialisation. Instead of relying on the LLC ID information parsed > >> separately only with ACPI PPTT elsewhere, migrate to use the similar > >> information from the cacheinfo. > >> > >> This is generic for both DT and ACPI systems. The ACPI LLC ID information > >> parsed separately can now be removed from arch specific code. > > > > Hey Sudeep, > > I bisected broken boot on PolarFire SoC to this patch in next-20220629 :/ > > I suspect the issue is a missing "next-level-cache" in the the dt: > > arch/riscv/boot/dts/microchip/mpfs.dtsi Good that I included this in -next, I had not received any feedback from RISC-V even after 5 iterations. I also see this DTS is very odd. It also states CPU0 doesn't have L1-D$ while the other 4 CPUs have L1-D$. Is that a mistake or is it the reality ? Another breakage in userspace cacheinfo sysfs entry of cpu0 has both I$ and D$. -- Regards, Sudeep