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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id d7-20020a5d5387000000b0021d5c52f4b4sm9912961wrv.34.2022.07.05.12.04.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jul 2022 12:04:49 -0700 (PDT) From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Brice Goglin Subject: [PATCH 1/5] riscv: dts: starfive: Add JH7100 CPU topology Date: Tue, 5 Jul 2022 20:04:32 +0100 Message-Id: <20220705190435.1790466-2-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 In-Reply-To: <20220705190435.1790466-1-mail@conchuod.ie> References: <20220705190435.1790466-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jonas Hahnfeld Add cpu-map binding to inform the kernel about the hardware topology of the CPU cores. Before this change, lstopo would report 1 core with 2 threads: Machine (7231MB total) Package L#0 NUMANode L#0 (P#0 7231MB) L2 L#0 (2048KB) + Core L#0 L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1) After this change, it correctly identifies two cores: Machine (7231MB total) Package L#0 NUMANode L#0 (P#0 7231MB) L2 L#0 (2048KB) L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) Signed-off-by: Jonas Hahnfeld Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 69f22f9aad9d..c617a61e26e2 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -17,7 +17,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + U74_0: cpu@0 { compatible = "sifive,u74-mc", "riscv"; reg = <0>; d-cache-block-size = <64>; @@ -42,7 +42,7 @@ cpu0_intc: interrupt-controller { }; }; - cpu@1 { + U74_1: cpu@1 { compatible = "sifive,u74-mc", "riscv"; reg = <1>; d-cache-block-size = <64>; @@ -66,6 +66,18 @@ cpu1_intc: interrupt-controller { #interrupt-cells = <1>; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&U74_0>; + }; + + core1 { + cpu = <&U74_1>; + }; + }; + }; }; osc_sys: osc_sys { -- 2.37.0