From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4844EC43334 for ; Fri, 8 Jul 2022 08:26:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237302AbiGHI0F (ORCPT ); Fri, 8 Jul 2022 04:26:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237138AbiGHI0C (ORCPT ); Fri, 8 Jul 2022 04:26:02 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 675C97969A for ; Fri, 8 Jul 2022 01:26:00 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6E21E1063; Fri, 8 Jul 2022 01:26:00 -0700 (PDT) Received: from bogus (unknown [10.57.39.193]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A11A53F792; Fri, 8 Jul 2022 01:25:54 -0700 (PDT) Date: Fri, 8 Jul 2022 09:24:43 +0100 From: Sudeep Holla To: Conor Dooley Cc: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J . Wysocki" , Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Atish Patra , Changbin Du , Heiko Stuebner , Philipp Tomsich , Rob Herring , Marc Zyngier , Viresh Kumar , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brice Goglin Subject: Re: [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology() Message-ID: <20220708082443.azoqvuj7afrg7ox7@bogus> References: <20220707220436.4105443-1-mail@conchuod.ie> <20220707220436.4105443-3-mail@conchuod.ie> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220707220436.4105443-3-mail@conchuod.ie> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 07, 2022 at 11:04:35PM +0100, Conor Dooley wrote: > From: Conor Dooley > > RISC-V & arm64 both use an almost identical method of filling in > default vales for arch topology. Create a weakly defined default > implementation with the intent of migrating both archs to use it. > > Signed-off-by: Conor Dooley > --- > drivers/base/arch_topology.c | 19 +++++++++++++++++++ > include/linux/arch_topology.h | 1 + > 2 files changed, 20 insertions(+) > > diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c > index 441e14ac33a4..07e84c6ac5c2 100644 > --- a/drivers/base/arch_topology.c > +++ b/drivers/base/arch_topology.c > @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid) > } > } > > +void __weak store_cpu_topology(unsigned int cpuid) I prefer to have this as default implementation. So just get the risc-v one pushed to upstream first(for v5.20) and get all the backports if required. Next cycle(i.e. v5.21), you can move both RISC-V and arm64. -- Regards, Sudeep