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From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To: <linux-kernel@vger.kernel.org>, <iommu@lists.linux.dev>
Cc: <joro@8bytes.org>, <robin.murphy@arm.com>, <vasant.hegde@amd.com>,
	<ashish.kalra@amd.com>, <jon.grimm@amd.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: [PATCH v4 1/9] iommu/amd: Change macro for IOMMU control register bit shift to decimal value
Date: Wed, 13 Jul 2022 17:56:43 -0500	[thread overview]
Message-ID: <20220713225651.20758-2-suravee.suthikulpanit@amd.com> (raw)
In-Reply-To: <20220713225651.20758-1-suravee.suthikulpanit@amd.com>

There is no functional change.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
 drivers/iommu/amd/amd_iommu_types.h | 42 ++++++++++++++---------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 40f52d02c5b9..7c830e3c7a91 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -143,27 +143,27 @@
 #define EVENT_FLAG_I		0x008
 
 /* feature control bits */
-#define CONTROL_IOMMU_EN        0x00ULL
-#define CONTROL_HT_TUN_EN       0x01ULL
-#define CONTROL_EVT_LOG_EN      0x02ULL
-#define CONTROL_EVT_INT_EN      0x03ULL
-#define CONTROL_COMWAIT_EN      0x04ULL
-#define CONTROL_INV_TIMEOUT	0x05ULL
-#define CONTROL_PASSPW_EN       0x08ULL
-#define CONTROL_RESPASSPW_EN    0x09ULL
-#define CONTROL_COHERENT_EN     0x0aULL
-#define CONTROL_ISOC_EN         0x0bULL
-#define CONTROL_CMDBUF_EN       0x0cULL
-#define CONTROL_PPRLOG_EN       0x0dULL
-#define CONTROL_PPRINT_EN       0x0eULL
-#define CONTROL_PPR_EN          0x0fULL
-#define CONTROL_GT_EN           0x10ULL
-#define CONTROL_GA_EN           0x11ULL
-#define CONTROL_GAM_EN          0x19ULL
-#define CONTROL_GALOG_EN        0x1CULL
-#define CONTROL_GAINT_EN        0x1DULL
-#define CONTROL_XT_EN           0x32ULL
-#define CONTROL_INTCAPXT_EN     0x33ULL
+#define CONTROL_IOMMU_EN	0
+#define CONTROL_HT_TUN_EN	1
+#define CONTROL_EVT_LOG_EN	2
+#define CONTROL_EVT_INT_EN	3
+#define CONTROL_COMWAIT_EN	4
+#define CONTROL_INV_TIMEOUT	5
+#define CONTROL_PASSPW_EN	8
+#define CONTROL_RESPASSPW_EN	9
+#define CONTROL_COHERENT_EN	10
+#define CONTROL_ISOC_EN		11
+#define CONTROL_CMDBUF_EN	12
+#define CONTROL_PPRLOG_EN	13
+#define CONTROL_PPRINT_EN	14
+#define CONTROL_PPR_EN		15
+#define CONTROL_GT_EN		16
+#define CONTROL_GA_EN		17
+#define CONTROL_GAM_EN		25
+#define CONTROL_GALOG_EN	28
+#define CONTROL_GAINT_EN	29
+#define CONTROL_XT_EN		50
+#define CONTROL_INTCAPXT_EN	51
 
 #define CTRL_INV_TO_MASK	(7 << CONTROL_INV_TIMEOUT)
 #define CTRL_INV_TO_NONE	0
-- 
2.32.0


  reply	other threads:[~2022-07-13 22:57 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-13 22:56 [PATCH v4 0/9] iommu/amd: Enforce IOMMU restrictions for SNP-enabled system Suravee Suthikulpanit
2022-07-13 22:56 ` Suravee Suthikulpanit [this message]
2022-07-13 22:56 ` [PATCH v4 2/9] iommu/amd: Introduce Support for Extended Feature 2 Register Suravee Suthikulpanit
2022-07-13 22:56 ` [PATCH v4 3/9] iommu/amd: Introduce global variable for storing common EFR and EFR2 Suravee Suthikulpanit
2022-07-13 22:56 ` [PATCH v4 4/9] iommu/amd: Process all IVHDs before enabling IOMMU features Suravee Suthikulpanit
2022-07-13 22:56 ` [PATCH v4 5/9] iommu/amd: Globally detect SNP support Suravee Suthikulpanit
2022-07-13 22:56 ` [PATCH v4 6/9] iommu/amd: Introduce function to check and enable SNP Suravee Suthikulpanit
2022-07-13 22:56 ` [PATCH v4 7/9] iommu/amd: Set translation valid bit only when IO page tables are in use Suravee Suthikulpanit
2022-07-13 22:56 ` [PATCH v4 8/9] iommu/amd: Do not support IOMMU_DOMAIN_IDENTITY after SNP is enabled Suravee Suthikulpanit
2022-07-15  8:46   ` Joerg Roedel
2022-07-13 22:56 ` [PATCH v4 9/9] iommu/amd: Do not support IOMMUv2 APIs when " Suravee Suthikulpanit
2022-07-15  8:44 ` [PATCH v4 0/9] iommu/amd: Enforce IOMMU restrictions for SNP-enabled system Joerg Roedel

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