From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00EC3C433EF for ; Fri, 15 Jul 2022 20:42:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230505AbiGOUmr (ORCPT ); Fri, 15 Jul 2022 16:42:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230339AbiGOUmj (ORCPT ); Fri, 15 Jul 2022 16:42:39 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5305187379 for ; Fri, 15 Jul 2022 13:42:38 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id i9-20020a258b09000000b0066efe437da6so4624258ybl.5 for ; Fri, 15 Jul 2022 13:42:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=EPwdfsc9LMe3xaxT7rQ2AwZ4mWZYsqTIzZwyJm21GaY=; b=hTQIEhNtwLcDTjuYElsz5q0eL249pESLhJ8EP2qPrdhFWAWD6W4lbyapYiA0Fp+y2h PqHx4qe9jc0K0fC8jJRNl2z5NXcy+FXNQFYnGbYMLcDt0P1UYL/OTXvp66EWn2xIAgvk J9ST5jj1zPPqHCAyn35zODw0XqDdQeHBiOcHWQuW3fr9YMXrhR1BBMv6PXgoUE6n0Umu 3X2MJwOc/DTaDbDpKm8WAMZXAeO8bVxa1PsPMxu9Ftd42dqJRNaCyslc7WQYq83VDDU+ jFlMt6ixZtv82rPGvEISQwQkIKT5n4+34EKeVGT2x+HR1ADC7t5zzQc5BhNSE4Kcf40V qk1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=EPwdfsc9LMe3xaxT7rQ2AwZ4mWZYsqTIzZwyJm21GaY=; b=wZaz4Tnywjs2mybnRJ8VZ6YImAR8vk3V8d2iPGmkcdemragb3ajKbLXddX6CMtA2jR D6eT9tA842boJHnIJBVaXlGaAXTbDDD4rgQsO4sGzBqx8ApFteaa/5GgzUlRU1PkdA0T iiQ+w0gjpeKCIQ4rlSbPzsZ8e+VW/C7aZs5q6DWm0mM2sddi7eb1V6bFw4lE9IAeyOUH 05NDi6SFVVE+rN7UQIk69uExOVR0JPrA3iBdpuYL2AMxoawh/wuvKtE/7BPO/Ju8T+Pt T0ScaVsRQLiqSsubxDoZrcgh3gP6r3nDcACEV/WlJW9CY0LlpV254x4V0m8ARiknhy7A C4nQ== X-Gm-Message-State: AJIora+IkMINu4MtshsxbmpuShsBjouj3gfRkTmTnpW4/xO1lcpF7dWx 28aZ2Ev1dluLnPMn2b1ZSntTd+ncNN4= X-Google-Smtp-Source: AGRyM1u6UpHh1N6KxJP2MAnf+tpvcvYp7Qkv9jqJ8abXF3dxaUvhIvXuqu2cY9+l6GUJZ+BhsNo+O9zcFNA= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:ca88:0:b0:66f:f681:4c3a with SMTP id a130-20020a25ca88000000b0066ff6814c3amr3426982ybg.582.1657917757506; Fri, 15 Jul 2022 13:42:37 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 15 Jul 2022 20:42:04 +0000 In-Reply-To: <20220715204226.3655170-1-seanjc@google.com> Message-Id: <20220715204226.3655170-3-seanjc@google.com> Mime-Version: 1.0 References: <20220715204226.3655170-1-seanjc@google.com> X-Mailer: git-send-email 2.37.0.170.g444d1eabd0-goog Subject: [PATCH v2 02/24] KVM: VMX: Drop bits 31:16 when shoving exception error code into VMCS From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Maxim Levitsky , Oliver Upton , Peter Shier Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Deliberately truncate the exception error code when shoving it into the VMCS (VM-Entry field for vmcs01 and vmcs02, VM-Exit field for vmcs12). Intel CPUs are incapable of handling 32-bit error codes and will never generate an error code with bits 31:16, but userspace can provide an arbitrary error code via KVM_SET_VCPU_EVENTS. Failure to drop the bits on exception injection results in failed VM-Entry, as VMX disallows setting bits 31:16. Setting the bits on VM-Exit would at best confuse L1, and at worse induce a nested VM-Entry failure, e.g. if L1 decided to reinject the exception back into L2. Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson Reviewed-by: Jim Mattson --- arch/x86/kvm/vmx/nested.c | 9 ++++++++- arch/x86/kvm/vmx/vmx.c | 11 ++++++++++- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 8c2c81406248..05c34a72c266 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -3822,7 +3822,14 @@ static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu *vcpu, u32 intr_info = nr | INTR_INFO_VALID_MASK; if (vcpu->arch.exception.has_error_code) { - vmcs12->vm_exit_intr_error_code = vcpu->arch.exception.error_code; + /* + * Intel CPUs will never generate an error code with bits 31:16 + * set, and more importantly VMX disallows setting bits 31:16 + * in the injected error code for VM-Entry. Drop the bits to + * mimic hardware and avoid inducing failure on nested VM-Entry + * if L1 chooses to inject the exception back to L2. + */ + vmcs12->vm_exit_intr_error_code = (u16)vcpu->arch.exception.error_code; intr_info |= INTR_INFO_DELIVER_CODE_MASK; } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index b0cc911a8f6f..d2b3d30d6afb 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1621,7 +1621,16 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu) kvm_deliver_exception_payload(vcpu); if (has_error_code) { - vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); + /* + * Despite the error code being architecturally defined as 32 + * bits, and the VMCS field being 32 bits, Intel CPUs and thus + * VMX don't actually supporting setting bits 31:16. Hardware + * will (should) never provide a bogus error code, but KVM's + * ABI lets userspace shove in arbitrary 32-bit values. Drop + * the upper bits to avoid VM-Fail, losing information that + * does't really exist is preferable to killing the VM. + */ + vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, (u16)error_code); intr_info |= INTR_INFO_DELIVER_CODE_MASK; } -- 2.37.0.170.g444d1eabd0-goog