From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B6E4C433EF for ; Fri, 22 Jul 2022 22:44:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237022AbiGVWo0 (ORCPT ); Fri, 22 Jul 2022 18:44:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236971AbiGVWoR (ORCPT ); Fri, 22 Jul 2022 18:44:17 -0400 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 649E6BB5 for ; Fri, 22 Jul 2022 15:44:16 -0700 (PDT) Received: by mail-pf1-x449.google.com with SMTP id p21-20020aa78615000000b00528d84505b5so2414381pfn.13 for ; Fri, 22 Jul 2022 15:44:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=9G8uQUSZj7v4UHpXueicxg4z7HLUkR6M06BpV0pfE2A=; b=BtnvUGhXo8FNJq4+dboCuzzQEcIKDkhpSyiqC+p0WVx8OKcRagSaCHp/9pjiPqY6AP pf1HYAVxTgofQOGxjB+But51yclF6DiPs5ZXNb7/jNHy7xWldiLIDn1WMsOo5uwTHYC4 DMk3wQckzpTtTEXC/sYuRcDmrpfX9IxbkQfovjSHSPkszIuS9/NnRNs6fyI1J/WEsmST i1n+sYALhVoOAM7IMsRyMWghXhfxM5YcHeNSZlePd+j7la3ou+X8gO5UVUXYg67Z5rJv kiWkF/jeKkHAWAKLcN04tv7ilK4g1A+f6e0tYlW8qaK/r28/p6ASChOVTTm5lM1ft+ul WGpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=9G8uQUSZj7v4UHpXueicxg4z7HLUkR6M06BpV0pfE2A=; b=ngPMvcJq++c7ZEPEzej7IfSSrrWnsqmFeh+scj9FHJHZMFFDVuq0usq/xeFqKy5e0v XzaG+sd+rIfMK2Q3/epXtV+wu5aiyywV39RXanY6P3m2IjoirknlKlH+65JxAsk6Nk/B 0MlyrwFrRbu3kIKb041wREE/DXcnsmn+r+XG1MWHny4PiAJRvvguxvOszXmDpbt2g7o4 1kseHuhFj0lKvawEk+Q4IsCNQjryJlYsYEASnwIJNd/52Lb1nu21esz96uM5VaQToU9M VaEgQ0ZtxtJLu0aPYE4e/J3BK/xIdH3bZP0o9RcWKvf4KKJHcFgZ7gZm+iCAPB3+9z/j crIg== X-Gm-Message-State: AJIora/A5CZO6MiE7K5BtAD41fiNpCknv2+gkKMEpRok7RUw9is5noRg DylcWa3bA91+C+LFwtvIaQ1bFmeBzeQ= X-Google-Smtp-Source: AGRyM1t9GNt4LECENs25Ww0TbI0BikLZMmC5OL2xSEWkDJpJyBU/9b5VWWYWdt3pFiWl/1WiNvrBWE+bApg= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:ab12:b0:16c:8d8a:c865 with SMTP id ik18-20020a170902ab1200b0016c8d8ac865mr1616901plb.145.1658529855990; Fri, 22 Jul 2022 15:44:15 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 22 Jul 2022 22:44:06 +0000 In-Reply-To: <20220722224409.1336532-1-seanjc@google.com> Message-Id: <20220722224409.1336532-3-seanjc@google.com> Mime-Version: 1.0 References: <20220722224409.1336532-1-seanjc@google.com> X-Mailer: git-send-email 2.37.1.359.gd136c6c3e2-goog Subject: [PATCH 2/5] KVM: VMX: Mark all PERF_GLOBAL_(OVF)_CTRL bits reserved if there's no vPMU From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Mark all MSR_CORE_PERF_GLOBAL_CTRL and MSR_CORE_PERF_GLOBAL_OVF_CTRL bits as reserved if there is no guest vPMU. The nVMX VM-Entry consistency checks do not check for a valid vPMU prior to consuming the masks via kvm_valid_perf_global_ctrl(), i.e. may incorrectly allow a non-zero mask to be loaded via VM-Enter or VM-Exit (well, attempted to be loaded, the actual MSR load will be rejected by intel_is_valid_msr()). Fixes: f5132b01386b ("KVM: Expose a version 2 architectural PMU to a guests") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 4bc098fbec31..6e355c5d2f40 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -527,6 +527,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->version = 0; pmu->reserved_bits = 0xffffffff00200000ull; pmu->raw_event_mask = X86_RAW_EVENT_MASK; + pmu->global_ctrl_mask = ~0ull; + pmu->global_ovf_ctrl_mask = ~0ull; pmu->fixed_ctr_ctrl_mask = ~0ull; pmu->pebs_enable_mask = ~0ull; pmu->pebs_data_cfg_mask = ~0ull; -- 2.37.1.359.gd136c6c3e2-goog