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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT041.mail.protection.outlook.com (10.13.172.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5482.10 via Frontend Transport; Fri, 29 Jul 2022 01:12:36 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Thu, 28 Jul 2022 20:12:20 -0500 Date: Thu, 28 Jul 2022 20:09:24 -0500 From: Michael Roth To: Sean Christopherson CC: Paolo Bonzini , , , Tom Lendacky Subject: Re: [PATCH 0/4] KVM: x86/mmu: MMIO caching bug fixes Message-ID: <20220729010924.zatnwgprojuqspna@amd.com> References: <20220728221759.3492539-1-seanjc@google.com> MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2022 01:12:36.4121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f342b6d-6e6b-4d73-6f7a-08da70ff6c79 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1675 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jul 28, 2022 at 10:17:55PM +0000, Sean Christopherson wrote: > Fix two bugs I introduced when adding the enable_mmio_caching module param. > > Bug #1 is that KVM unintentionally makes disabling caching due to a config > incompatibility "sticky", e.g. disabling caching because there are no > reserved PA bits prevents KVM from enabling when "switching" to an EPT > config (doesn't rely on PA bits) or when SVM adjusts the MMIO masks to > account for C-bit shenanigans (even if MAXPHYADDR=52 and C-bit=51, there > can be reserved PA bits due to the "real" MAXPHYADDR being reduced). > > Bug #2 is that KVM doesn't explicitly check that MMIO caching is enabled > when doing SEV-ES setup. Prior to the module param, MMIO caching was > guaranteed when SEV-ES could be enabled as SEV-ES-capable CPUs effectively > guarantee there will be at least one reserved PA bit (see above). With > the module param, userspace can explicitly disable MMIO caching, thus > silently breaking SEV-ES. > > I believe I tested all combinations of things getting disabled and enabled > by hacking kvm_mmu_reset_all_pte_masks() to disable MMIO caching on a much > lower MAXPHYADDR, e.g. 43 instead of 52. That said, definitely wait for a > thumbs up from the AMD folks before queueing. I tested the below systems/configurations and everything looks good to me. Thanks for the quick fix! AMD Milan, MAXPHYADDR = 48 bits, kvm.mmio_caching=on (on by default) normal: pass SEV: pass SEV-ES: pass AMD Milan, MAXPHYADDR = 48 bits, kvm.mmio_caching=off normal: pass SEV: pass SEV-ES: fail (as expected, since kvm_amd.sev_es gets forced to off) AMD unreleased, MAXPHYADDR = 52 bits, kvm.mmio_caching=on (on by default) normal: pass SEV: pass SEV-ES: pass AMD unreleased, MAXPHYADDR = 52 bits, kvm.mmio_caching=off normal: pass SEV: pass SEV-ES: fail (as expected, since kvm_amd.sev_es gets forced to off) > > Sean Christopherson (4): > KVM: x86: Tag kvm_mmu_x86_module_init() with __init > KVM: x86/mmu: Fully re-evaluate MMIO caching when SPTE masks change > KVM: SVM: Adjust MMIO masks (for caching) before doing SEV(-ES) setup > KVM: SVM: Disable SEV-ES support if MMIO caching is disable Series: Tested-by: Michael Roth -Mike