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[70.27.3.10]) by smtp.gmail.com with ESMTPSA id u9-20020a05620a454900b006b259b5dd12sm1584531qkp.53.2022.07.28.18.40.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 28 Jul 2022 18:40:48 -0700 (PDT) From: Peter Xu To: linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Huang Ying , peterx@redhat.com, Andrea Arcangeli , Andrew Morton , "Kirill A . Shutemov" , Nadav Amit , Hugh Dickins , David Hildenbrand , Vlastimil Babka Subject: [PATCH RFC 4/4] mm/x86: Define __ARCH_SWP_OFFSET_BITS Date: Thu, 28 Jul 2022 21:40:41 -0400 Message-Id: <20220729014041.21292-5-peterx@redhat.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220729014041.21292-1-peterx@redhat.com> References: <20220729014041.21292-1-peterx@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This will enable the new migration young bit for all x86 systems for both 32 bits and 64 bits systems (including PAE). Signed-off-by: Peter Xu --- arch/x86/include/asm/pgtable-2level.h | 6 ++++++ arch/x86/include/asm/pgtable-3level.h | 7 +++++++ arch/x86/include/asm/pgtable_64.h | 5 +++++ 3 files changed, 18 insertions(+) diff --git a/arch/x86/include/asm/pgtable-2level.h b/arch/x86/include/asm/pgtable-2level.h index 60d0f9015317..6e70833feb69 100644 --- a/arch/x86/include/asm/pgtable-2level.h +++ b/arch/x86/include/asm/pgtable-2level.h @@ -95,6 +95,12 @@ static inline unsigned long pte_bitop(unsigned long value, unsigned int rightshi #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low }) #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val }) +/* + * This defines how many bits we have in the arch specific swp offset. + * For 32 bits vanilla systems the pte and swap entry has the same size. + */ +#define __ARCH_SWP_OFFSET_BITS (sizeof(swp_entry_t) - SWP_TYPE_BITS) + /* No inverted PFNs on 2 level page tables */ static inline u64 protnone_mask(u64 val) diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h index 28421a887209..8dbf29b51f8b 100644 --- a/arch/x86/include/asm/pgtable-3level.h +++ b/arch/x86/include/asm/pgtable-3level.h @@ -287,6 +287,13 @@ static inline pud_t native_pudp_get_and_clear(pud_t *pudp) #define __pte_to_swp_entry(pte) (__swp_entry(__pteval_swp_type(pte), \ __pteval_swp_offset(pte))) +/* + * This defines how many bits we have in the arch specific swp offset. + * Here since we're putting the 32 bits swap entry into 64 bits pte, the + * limitation is the 32 bits swap entry minus the swap type field. + */ +#define __ARCH_SWP_OFFSET_BITS (sizeof(swp_entry_t) - SWP_TYPE_BITS) + #include #endif /* _ASM_X86_PGTABLE_3LEVEL_H */ diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index e479491da8d5..1714f0ded1db 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h @@ -217,6 +217,11 @@ static inline void native_pgd_clear(pgd_t *pgd) /* We always extract/encode the offset by shifting it all the way up, and then down again */ #define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT+SWP_TYPE_BITS) +/* + * This defines how many bits we have in the arch specific swp offset. 64 + * bits systems have both swp_entry_t and pte in 64 bits. + */ +#define __ARCH_SWP_OFFSET_BITS (BITS_PER_LONG - SWP_OFFSET_SHIFT) #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) -- 2.32.0