From: "Daniel Glöckner" <dg@emlix.com>
To: Ivan Bornyakov <i.bornyakov@metrotek.ru>
Cc: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com,
trix@redhat.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-fpga@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
system@metrotek.ru,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v5 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr
Date: Fri, 29 Jul 2022 11:01:24 +0200 [thread overview]
Message-ID: <20220729090123.GA28299@homes.emlix.com> (raw)
In-Reply-To: <20220719112335.9528-3-i.bornyakov@metrotek.ru>
Hi,
On Tue, Jul 19, 2022 at 02:23:35PM +0300, Ivan Bornyakov wrote:
> +properties:
> + compatible:
> + enum:
> + - lattice,ecp5-fpga-mgr
Since this driver uses the same interface as the existing
drivers/fpga/machxo2-spi.c driver, wouldn't it be advisable to use a
similar compatible id, i.e. lattice,ecp5-slave-spi?
> +required:
> + - compatible
> + - reg
> + - program-gpios
> + - init-gpios
> + - done-gpios
I think some of the GPIOs can be made optional by reading the status
register or using the refresh command, assuming the slave spi interface
stayed enabled after previous programming and we are not dealing with
several chained FPGAs. But that can of course be left as an exercise for
other developers.
Best regards,
Daniel
next prev parent reply other threads:[~2022-07-29 9:08 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-19 11:23 [PATCH v5 0/2] Lattice ECP5 FPGA manager Ivan Bornyakov
2022-07-19 11:23 ` [PATCH v5 1/2] fpga: ecp5-spi: add " Ivan Bornyakov
2022-07-29 12:41 ` Daniel Glöckner
2022-08-01 7:24 ` Daniel Glöckner
2022-08-09 6:54 ` Ivan Bornyakov
2022-07-19 11:23 ` [PATCH v5 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr Ivan Bornyakov
2022-07-29 9:01 ` Daniel Glöckner [this message]
2022-07-29 14:57 ` Xu Yilun
2022-07-29 16:33 ` Ivan Bornyakov
2022-07-29 17:49 ` Daniel Glöckner
2022-07-21 7:44 ` [PATCH v5 0/2] Lattice ECP5 FPGA manager Xu Yilun
2022-07-21 8:54 ` Ivan Bornyakov
2022-07-27 6:00 ` Ivan Bornyakov
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