From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3A09C19F2D for ; Wed, 3 Aug 2022 19:27:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238167AbiHCT1I (ORCPT ); Wed, 3 Aug 2022 15:27:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231508AbiHCT1E (ORCPT ); Wed, 3 Aug 2022 15:27:04 -0400 Received: from mail-pg1-x549.google.com (mail-pg1-x549.google.com [IPv6:2607:f8b0:4864:20::549]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1D18564E5 for ; Wed, 3 Aug 2022 12:27:03 -0700 (PDT) Received: by mail-pg1-x549.google.com with SMTP id d31-20020a631d1f000000b0041a5a805e26so7111833pgd.16 for ; Wed, 03 Aug 2022 12:27:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:mime-version:message-id:date:reply-to:from:to:cc; bh=3RPOTZgLH8z1mj6S/J2PJvuGpfhZNmF41DEbta7HrMo=; b=gKuIIBdvQdBJu4sMYgx0Q90wW6lAC9OxXICWsrcsxMFPRuEUESQwb5lFSQVlxB5M3l KYvk4/WS21iPidCi1NOprQmF5glOHs1jagHWpFq4vyPuxvEGlvDBSF3G/SEIARiwW58W dkcwKi1TGOe2JtSdnws1BPabQEsQa68tBLCq1ON+yguApZeW0273w6rIIo8KHUtOJ0oE abP2CCLzkEMHdbdIn8XM6a700vkIVxoQNYLM28ri08U8AXVy3PGSJ/cmn39/4eejnV24 lXnpQIMPF/jz6Sg11yUn1r/RGmjtK44kIbygKPZBdd8Vrm7S1QZ/vpaPwiQl7e1TzuKn cvlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:mime-version:message-id:date:reply-to :x-gm-message-state:from:to:cc; bh=3RPOTZgLH8z1mj6S/J2PJvuGpfhZNmF41DEbta7HrMo=; b=SHFXXDJ0qw0m/ryLlbYu1gGqnI4WrKqP238qlVeYNcyQyBZXgyK+mpK0aclimS4WJR Foddrm8gIfnP1xZfng7wdJcgQlCl6K2nnSRHyXCHVxvN5inqsk9fbywaWqBX00wkgZ0e noljOVXHHwQYurXiLsoyu6RG9ZJBcyUVkzYGfPccoPi1s+KhGoStHva8NLnckT3KU6oL F83qI5X8BlrojdgeS4MhaFqsi1IVsyLXD/mjn0yhY+aVHYFvygp0lG568NBnerqgAbmN o1VzUqJ1aLku2uUuvlCdMzLOhI2eFD/q7+b18PUn4j8/CcCWZ4BIscgoRO57q/+brbcy a8jw== X-Gm-Message-State: ACgBeo0p0/WG3GdfnIlcxBsXQ87pPOJJ0jjpEUquizN6F2VmuskKS4sM aRPkwmFmdmFZraWFIgZGMV1uDAjo7j0= X-Google-Smtp-Source: AA6agR5/G+xmOFeILNiqYjsu2HB21yEsKdqFRR0RpP9Yl20POWePtSeiNqhqUeJqaXc6xllutDPlQynosOU= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:903:32d2:b0:16e:dfed:b4b6 with SMTP id i18-20020a17090332d200b0016edfedb4b6mr18139404plr.108.1659554823230; Wed, 03 Aug 2022 12:27:03 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 3 Aug 2022 19:26:51 +0000 Message-Id: <20220803192658.860033-1-seanjc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.37.1.559.g78731f0fdb-goog Subject: [PATCH v2 0/7] KVM: x86: Intel PERF_CAPABILITIES fixes and cleanups From: Sean Christopherson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Like Xu Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Bug fixes and cleanups related to KVM's handling of PERF_CAPABILITIES. Bug #1 - Refresh KVM's vPMU after userspace writes PERF_CAPABILITIES, and then leverage that fix to avoiding checking guest_cpuid_has(X86_FEATURE_PDCM) during VM-Enter, which is slow enough that it shows up in perf traces[*]. Bug #2 - Don't advertise PMU_CAP_LBR_FMT to userspace if perf has disabled LBRs, e.g. because probing one or more LBR MSRs during setup hit a #GP. The non-KVM patches remove unnecessary stubs and unreachable error paths, which allows for a cleaner fix for bug #2. [*] https://gist.github.com/avagin/f50a6d569440c9ae382281448c187f4e v2: - Add patches to fix bug #2. [Like] - Add a patch to clean up the capability check. - Tweak the changelog for the PMU refresh bug fix to call out that KVM should disallow changing feature MSRs after KVM_RUN. [Like] v1: https://lore.kernel.org/all/20220727233424.2968356-1-seanjc@google.com Sean Christopherson (7): KVM: x86: Refresh PMU after writes to MSR_IA32_PERF_CAPABILITIES perf/x86/core: Remove unnecessary stubs provided for KVM-only helpers perf/x86/core: Drop the unnecessary return value from x86_perf_get_lbr() KVM: VMX: Advertise PMU LBRs if and only if perf supports LBRs KVM: VMX: Use proper type-safe functions for vCPU => LBRs helpers KVM: VMX: Adjust number of LBR records for PERF_CAPABILITIES at refresh KVM: VMX: Simplify capability check when handling PERF_CAPABILITIES write arch/x86/events/intel/lbr.c | 6 +--- arch/x86/include/asm/perf_event.h | 55 ++++++++----------------------- arch/x86/kvm/vmx/capabilities.h | 5 ++- arch/x86/kvm/vmx/pmu_intel.c | 12 ++----- arch/x86/kvm/vmx/vmx.c | 6 ++-- arch/x86/kvm/vmx/vmx.h | 53 +++++++++++++++++------------ arch/x86/kvm/x86.c | 4 +-- 7 files changed, 58 insertions(+), 83 deletions(-) base-commit: 93472b79715378a2386598d6632c654a2223267b -- 2.37.1.559.g78731f0fdb-goog