From: ira.weiny@intel.com
To: Rik van Riel <riel@surriel.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@intel.com>
Cc: Ira Weiny <ira.weiny@intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@fb.com
Subject: [PATCH 3/3] x86/mm: Store CPU info on exception entry
Date: Wed, 10 Aug 2022 19:49:03 -0700 [thread overview]
Message-ID: <20220811024903.178925-4-ira.weiny@intel.com> (raw)
In-Reply-To: <20220811024903.178925-1-ira.weiny@intel.com>
From: Ira Weiny <ira.weiny@intel.com>
x86 has auxiliary pt_regs space available to store information on the
stack during exceptions. This information is easier to obtain and store
within C code.
The CPU information of a page fault is useful in determining where bad
CPUs are in a large data center.
Store the CPU on page fault entry and use it later.
Cc: Rik van Riel <riel@surriel.com>
Suggested-by: Borislav Petkov <bp@alien8.de>
Suggested-by: Dave Hansen <dave.hansen@intel.com>
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes from RFC:
New patch combining 2 and 5 from original series and modified.
Boris/Thomas - eliminate generic calls to save the cpu and call
only from exc_page_fault
---
arch/x86/Kconfig | 2 +-
arch/x86/include/asm/ptrace.h | 1 +
arch/x86/mm/fault.c | 12 ++++++++++--
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5a0b6ee49cb4..e4a04406be2c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1874,7 +1874,7 @@ config X86_INTEL_MEMORY_PROTECTION_KEYS
config ARCH_HAS_PTREGS_AUXILIARY
depends on X86_64
- bool
+ def_bool y
choice
prompt "TSX enable mode"
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 5a9c85893459..b403b469996f 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -97,6 +97,7 @@ struct pt_regs {
* ARCH_HAS_PTREGS_AUXILIARY. Failure to do so will result in a build failure.
*/
struct pt_regs_auxiliary {
+ int cpu;
};
struct pt_regs_extended {
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index dbc6a2e08a96..0aa420cd7874 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -768,9 +768,9 @@ static inline void
show_signal_msg(struct pt_regs *regs, unsigned long error_code,
unsigned long address, struct task_struct *tsk)
{
+ struct pt_regs_auxiliary *aux_pt_regs = &to_extended_pt_regs(regs)->aux;
const char *loglvl = task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG;
- /* This is a racy snapshot, but it's better than nothing. */
- int cpu = raw_smp_processor_id();
+ int cpu = aux_pt_regs->cpu;
if (!unhandled_signal(tsk, SIGSEGV))
return;
@@ -1507,6 +1507,13 @@ handle_page_fault(struct pt_regs *regs, unsigned long error_code,
}
}
+noinstr static void aux_pt_regs_save_cpu(struct pt_regs *regs)
+{
+ struct pt_regs_auxiliary *aux_pt_regs = &to_extended_pt_regs(regs)->aux;
+
+ aux_pt_regs->cpu = raw_smp_processor_id();
+}
+
DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault)
{
unsigned long address = read_cr2();
@@ -1550,6 +1557,7 @@ DEFINE_IDTENTRY_RAW_ERRORCODE(exc_page_fault)
*/
state = irqentry_enter(regs);
+ aux_pt_regs_save_cpu(regs);
instrumentation_begin();
handle_page_fault(regs, error_code, address);
instrumentation_end();
--
2.35.3
next prev parent reply other threads:[~2022-08-11 2:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-11 2:49 [PATCH 0/3] Print CPU at segfault time ira.weiny
2022-08-11 2:49 ` [PATCH 1/3] x86,mm: print likely " ira.weiny
2022-08-11 2:49 ` [PATCH 2/3] x86/entry: Add auxiliary pt_regs space ira.weiny
2022-08-11 2:49 ` ira.weiny [this message]
2022-09-02 3:15 ` [PATCH 0/3] Print CPU at segfault time Ira Weiny
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