From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A3BCC32771 for ; Fri, 19 Aug 2022 09:54:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347631AbiHSJyy (ORCPT ); Fri, 19 Aug 2022 05:54:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346996AbiHSJyp (ORCPT ); Fri, 19 Aug 2022 05:54:45 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 991E5BD09E; Fri, 19 Aug 2022 02:54:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660902884; x=1692438884; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=LHd+4+ztyLleLhRkBC+IDhKqnrDiduTJ+MVOjUQ9LfU=; b=bUDOOZDoz2GMeJyqdXuf+oU98eFB2dEbkJoEePg1zb1k8SPZDp/0mtAW iQGnBkt0XKT/yd5ZNgh9zLDgGNzNN++Ifq9i04Mu3ANFSjgsbWfzkEoWo qoeMZ/yb8iCR/OzNPMYogQ41mhvqZkGBYRJOg+WehjIrXV+2zT4DvdnMv tzBG0tBTGnk4Z3d256mdq7LgaNgv/IzsCJ5srRoUxjxCp6yxCBXgl2NHq G174xOBHkLKZBPKvUYVhxW4hhO9039K3wA1bflACZ6Woes3x8381iSokr qeEgFRGX1fhieZOwiI/If9fw8ZwJofaGzDr9cGhXAQh3erwFeyq+7iZH2 w==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="187175524" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 02:54:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 02:54:32 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 02:54:30 -0700 From: Conor Dooley To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Conor Dooley , Philipp Zabel , Daire McNamara CC: Paul Walmsley , Albert Ou , , , , Subject: [PATCH v3 00/13] PolarFire SoC reset controller & clock cleanups Date: Fri, 19 Aug 2022 10:53:08 +0100 Message-ID: <20220819095320.40006-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hey all, Kinda two things happening in this series, but I sent it together to ensure the second part would apply correctly. The first is the reset controller that I promised after discovering the issue triggered by CONFIG_PM & the phy not coming up correctly. I have now removed all the messing with resets from clock enable/disable functions & now use the aux bus to set up a reset controller driver. Since I needed something to test it, I hooked up the reset for the Cadence MACB on PolarFire SoC. This was been split into a second series for v2 (and is now in v6.0-rcN): https://lore.kernel.org/all/20220704114511.1892332-1-conor.dooley@microchip.com/ The second part adds rate control for the MSS PLL clock, followed by some simplifications to the driver & conversions of some custom structs to the corresponding structs in the framework. I'll take the dts patch myself when the rest of this is accepted. Thanks, Conor. Changes since v2: - reorder reset Makefile/Kconfig entries - fix a pre-existing bug exposed by clang with this series applied - add Padmarao who co-authored the original driver to the authors Conor Dooley (13): clk: microchip: mpfs: fix clk_cfg array bounds violation dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: add reset controller reset: add polarfire soc reset support MAINTAINERS: add polarfire soc reset controller riscv: dts: microchip: add mpfs specific macb reset support clk: microchip: mpfs: add MSS pll's set & round rate clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: update module authorship & licencing .../bindings/clock/microchip,mpfs.yaml | 17 +- MAINTAINERS | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +- drivers/clk/microchip/Kconfig | 1 + drivers/clk/microchip/clk-mpfs.c | 386 +++++++++--------- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 2 +- drivers/reset/reset-mpfs.c | 157 +++++++ include/soc/microchip/mpfs.h | 8 + 9 files changed, 391 insertions(+), 195 deletions(-) create mode 100644 drivers/reset/reset-mpfs.c base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 -- 2.36.1