tree:   https://github.com/AsahiLinux/linux pr/46
head:   5952de58993c87e5e5797ac37ef4f7364ac5ef37
commit: fede0e659aa9b0d19c539a78acd458efeb3d5684 [21/34] wip: ASoC: cs42l84: Start new codec driver
config: nios2-randconfig-r014-20220821
compiler: nios2-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/AsahiLinux/linux/commit/fede0e659aa9b0d19c539a78acd458efeb3d5684
        git remote add asahilinux https://github.com/AsahiLinux/linux
        git fetch --no-tags asahilinux pr/46
        git checkout fede0e659aa9b0d19c539a78acd458efeb3d5684
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=nios2 SHELL=/bin/bash kernel/ sound/soc/codecs/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   sound/soc/codecs/cs42l84.c: In function 'cs42l84_pll_config':
>> sound/soc/codecs/cs42l84.c:371:17: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
     371 |                 FIELD_PREP(CS42L84_ASP_FSYNC_CTL2_BCLK_PERIOD_LO, fsync & 0x7f));
         |                 ^~~~~~~~~~
   cc1: some warnings being treated as errors


vim +/FIELD_PREP +371 sound/soc/codecs/cs42l84.c

   330	
   331	static int cs42l84_pll_config(struct snd_soc_component *component)
   332	{
   333		struct cs42l84_private *cs42l84 = snd_soc_component_get_drvdata(component);
   334		int i;
   335		u32 clk;
   336		u32 fsync;
   337	
   338		clk = cs42l84->bclk;
   339	
   340		/* Don't reconfigure if there is an audio stream running */
   341		if (cs42l84->stream_use) {
   342			if (pll_ratio_table[cs42l84->pll_config].bclk == clk)
   343				return 0;
   344			else
   345				return -EBUSY;
   346		}
   347	
   348		for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
   349			if (pll_ratio_table[i].bclk == clk) {
   350				cs42l84->pll_config = i;
   351				break;
   352			}
   353		}
   354	
   355		if (i == ARRAY_SIZE(pll_ratio_table))
   356			return -EINVAL;
   357	
   358		/* Set up the LRCLK */
   359		fsync = clk / cs42l84->srate;
   360		if (((fsync * cs42l84->srate) != clk)
   361				|| ((fsync % 2) != 0)) {
   362			dev_err(component->dev,
   363				"Unsupported bclk %d/sample rate %d\n",
   364				clk, cs42l84->srate);
   365			return -EINVAL;
   366		}
   367	
   368		/* Set the LRCLK period */
   369		snd_soc_component_update_bits(component, CS42L84_ASP_FSYNC_CTL2,
   370			CS42L84_ASP_FSYNC_CTL2_BCLK_PERIOD_LO,
 > 371			FIELD_PREP(CS42L84_ASP_FSYNC_CTL2_BCLK_PERIOD_LO, fsync & 0x7f));
   372		snd_soc_component_update_bits(component, CS42L84_ASP_FSYNC_CTL3,
   373			CS42L84_ASP_FSYNC_CTL3_BCLK_PERIOD_HI,
   374			FIELD_PREP(CS42L84_ASP_FSYNC_CTL3_BCLK_PERIOD_HI, fsync >> 7));
   375	
   376		/* Save what the MCLK will be */
   377		switch (pll_ratio_table[i].mclk_int) {
   378		case 12000000:
   379			cs42l84->pll_mclk_f = CS42L84_CCM_CTL1_MCLK_F_12MHZ;
   380			break;
   381		case 12288000:
   382			cs42l84->pll_mclk_f = CS42L84_CCM_CTL1_MCLK_F_12_288KHZ;
   383			break;
   384		case 24000000:
   385			cs42l84->pll_mclk_f = CS42L84_CCM_CTL1_MCLK_F_24MHZ;
   386			break;
   387		case 24576000:
   388			cs42l84->pll_mclk_f = CS42L84_CCM_CTL1_MCLK_F_24_576KHZ;
   389			break;
   390		}
   391	
   392		if (pll_ratio_table[i].mclk_src_sel) {
   393			/* Configure PLL */
   394			snd_soc_component_update_bits(component,
   395				CS42L84_CCM_CTL3, CS42L84_CCM_CTL3_REFCLK_DIV,
   396				FIELD_PREP(CS42L84_CCM_CTL3_REFCLK_DIV, pll_ratio_table[i].bclk_prediv));
   397			snd_soc_component_write(component,
   398				CS42L84_PLL_DIV_INT,
   399				pll_ratio_table[i].pll_div_int);
   400			snd_soc_component_write(component,
   401				CS42L84_PLL_DIV_FRAC0,
   402				pll_ratio_table[i].pll_div_frac);
   403			snd_soc_component_write(component,
   404				CS42L84_PLL_DIV_FRAC1,
   405				pll_ratio_table[i].pll_div_frac >> 8);
   406			snd_soc_component_write(component,
   407				CS42L84_PLL_DIV_FRAC2,
   408				pll_ratio_table[i].pll_div_frac >> 16);
   409			snd_soc_component_update_bits(component,
   410				CS42L84_PLL_CTL1, CS42L84_PLL_CTL1_MODE,
   411				FIELD_PREP(CS42L84_PLL_CTL1_MODE, pll_ratio_table[i].pll_mode));
   412			snd_soc_component_write(component,
   413				CS42L84_PLL_DIVOUT,
   414				pll_ratio_table[i].pll_divout);
   415	
   416			snd_soc_component_update_bits(component,
   417				CS42L84_PLL_CTL1, CS42L84_PLL_CTL1_EN,
   418				CS42L84_PLL_CTL1_EN);
   419		}
   420	
   421		return 0;
   422	}
   423	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp