From: Zong Li <zong.li@sifive.com>
To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, greentime.hu@sifive.com,
conor.dooley@microchip.com, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache
Date: Mon, 29 Aug 2022 06:22:00 +0000 [thread overview]
Message-ID: <20220829062202.3287-2-zong.li@sifive.com> (raw)
In-Reply-To: <20220829062202.3287-1-zong.li@sifive.com>
Since composible cache may be L3 cache if private L2 cache exists, it
should use its original name composible cache to prevent confusion.
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
---
.../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
similarity index 92%
rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 69cdab18d629..1a64a5384e36 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -12,8 +12,8 @@ maintainers:
- Paul Walmsley <paul.walmsley@sifive.com>
description:
- The SiFive Level 2 Cache Controller is used to provide access to fast copies
- of memory for masters in a Core Complex. The Level 2 Cache Controller also
+ The SiFive Composable Cache Controller is used to provide access to fast copies
+ of memory for masters in a Core Complex. The Composable Cache Controller also
acts as directory-based coherency manager.
All the properties in ePAPR/DeviceTree specification applies for this platform.
@@ -27,6 +27,7 @@ select:
enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - sifive,ccache0
required:
- compatible
@@ -37,6 +38,7 @@ properties:
- enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
+ - sifive,ccache0
- const: cache
cache-block-size:
--
2.17.1
next prev parent reply other threads:[~2022-08-29 6:22 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-29 6:21 [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE Zong Li
2022-08-29 6:22 ` Zong Li [this message]
2022-08-29 6:45 ` [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache Conor.Dooley
2022-08-29 7:38 ` Zong Li
2022-08-29 18:42 ` Rob Herring
2022-08-30 2:57 ` Zong Li
2022-10-07 2:58 ` Palmer Dabbelt
2022-10-07 3:51 ` Zong Li
2022-08-29 6:22 ` [PATCH 2/3] soc: sifive: l2 cache: Rename " Zong Li
2022-08-29 7:05 ` Conor.Dooley
2022-08-29 8:40 ` Zong Li
2022-08-30 8:41 ` Conor.Dooley
2022-08-31 5:31 ` Zong Li
2022-08-30 8:18 ` Ben Dooks
2022-08-29 6:22 ` [PATCH 3/3] EDAC/sifive: use sifive_ccache instead of sifive_l2 Zong Li
2022-10-07 2:58 ` Palmer Dabbelt
2022-08-30 7:59 ` [PATCH 0/3] Rename sifive L2 cache to sifive CCACHE Ben Dooks
2022-08-31 8:23 ` Zong Li
2022-08-30 8:26 ` [PATCH] soc: sifive: ccache: reduce printing on init Ben Dooks
2022-08-30 16:30 ` Conor.Dooley
2022-08-30 17:03 ` Ben Dooks
2022-08-31 5:22 ` Zong Li
2022-08-31 15:55 ` Ben Dooks
2022-09-01 8:34 ` Zong Li
2022-08-30 8:36 ` [PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache Ben Dooks
2022-08-30 12:47 ` Rob Herring
2022-08-30 12:51 ` [RESEND PATCH] " Ben Dooks
2022-08-30 12:56 ` Conor.Dooley
2022-08-30 12:58 ` Ben Dooks
2022-08-30 13:49 ` Conor.Dooley
2022-08-30 16:49 ` Ben Dooks
2022-08-30 17:08 ` Conor.Dooley
2022-08-31 5:17 ` Zong Li
2022-08-31 6:25 ` Conor.Dooley
2022-09-02 19:36 ` Rob Herring
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