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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id z11-20020a170902cccb00b00173cfaed233sm7296332ple.62.2022.09.12.23.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:18:23 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v5 0/7] Use composable cache instead of L2 cache Date: Tue, 13 Sep 2022 06:18:10 +0000 Message-Id: <20220913061817.22564-1-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since composable cache may be L3 cache if private L2 cache exists, we should use its original name "composable cache" to prevent confusion. This patchset contains the modification which is related to ccache, such as DT binding and EDAC driver. The DT binding is based on top of Conor's patch, it has got ready for merging, and it looks that it would be taken into the next few 6.0-rc version. If there is any change, the next version of this series will be posted as well. https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@conchuod.ie/ Change log in v5: - Add a patch to modify aux vector for sysconf Change log in v4: - Change the return value from from ENODEV to ENOENT - Apply pr_fmt refinement to all pr_err Change log in v3: - Merged the EDAC patch into L2 rename patch - Define the macro for register shift and refine the relative code - Fix some indent issues Change log in v2: - Separate the rename and diff to different patches - Rebase the dt-bindings based on Conor's modification - Include the patches of Ben for refinement of printing message Ben Dooks (2): soc: sifive: ccache: reduce printing on init soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes Greentime Hu (2): soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. riscv: Add cache information in AUX vector Zong Li (3): dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: define the macro for the register shifts ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 ++- arch/riscv/include/asm/elf.h | 4 + arch/riscv/include/uapi/asm/auxvec.h | 4 +- drivers/edac/Kconfig | 2 +- drivers/edac/sifive_edac.c | 12 +- drivers/soc/sifive/Kconfig | 6 +- drivers/soc/sifive/Makefile | 2 +- .../{sifive_l2_cache.c => sifive_ccache.c} | 200 ++++++++++-------- .../{sifive_l2_cache.h => sifive_ccache.h} | 16 +- 9 files changed, 158 insertions(+), 116 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%) rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (31%) rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%) -- 2.17.1